Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 955

Bits Name
31–30 PTS Port transceiver select. This register bit is used to control which parallel transceiver interface is selected.
00 UTMI parallel interface
01 Reserved, should be cleared
10 ULPI parallel interface
11 Reserved
This bit is not defined in the EHCI specification.
29 — Reserved, should be cleared
28 — Reserved
27–26 PSPD Port speed. This read-only register field indicates the speed at which the port is operating.
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
25 — Reserved, should be cleared
24 PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS
port. This is useful for testing FS configurations with a HS host, hub or device.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
23 PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Host mode:
• The PHY can be put into low power suspend—when the downstream device has been put into suspend
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
Device mode:
• The PHY can be put into low power suspend—when the device is not running (USBCMD[RS] = 0b) or
suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following
registers should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0,
ENDPTCTRL1, ENDPTCTRL2.
22 WKOC Wake on over-current enable. Writing this bit to a one enables the port to be sensitive to over-current
conditions as wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is (OTG/host mode only) for use by an external power control circuit.
21 WKDS Wake on disconnect enable. Writing this bit to a one enables the port to be sensitive to device disconnects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-23. PORTSC Register Field Descriptions
Description
Universal Serial Bus Interface
16-27