Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 939

Offset 0x2_3120
15
R
W
Reset 0 0 0
Table 16-8 provides bit descriptions for the DCIVERSION register.
Bits Name
15–0 DCIVERSION
16.3.1.6 Device Controller Capability Parameters (DCCPARAMS)—Non-EHCI
This register is not defined in the EHCI specification. This register describes the overall host/device
capability of the DR module.
Offset 0x2_3124
31
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-7. Device Control Capability Parameters (DCCPARAMS)
Table 16-9 provides bit descriptions for the DCCPARAMS register.
Bits Name
31–9 — Reserved, should be cleared.
8 HC Host capable. Always 1, indicating the USB DR controller can operate as an EHCI compatible USB 2.0 host
7 DC Device capable. Always 1, indicating the USB DR controller can operate as an USB 2.0 device.
1 Device capability.
0 No device capability (host only).
6–5 — Reserved, should be cleared.
4–0 DEN Device endpoint number. Indicates the number of endpoints built into the device controller. Always 0x3.
16.3.2 Operational Registers
The operational registers are comprised of dynamic control or status registers that may be read-only,
read/write, or read/write-1-to-clear. The following sections define the operational registers.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
0 0 0 0
Figure 16-6. Device Interface Version (DCIVERSION)
Table 16-8. DCIVERSION Register Field Descriptions
Device interface revision number.
Figure 16-7 shows the DCCPARAMS register.
—
Table 16-9. DCCPARAMS Register Field Descriptions
DCIVERSION
0 0 0 0
Description
9 8
HC DC
1
Description
Universal Serial Bus Interface
Access: Read-only
0 0 0 0
Access: Read-only
7 6 5 4
DEN
—
1 0 0 0 0 0 1
0
1
0
1
16-11