Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 732

Enhanced Three-Speed Ethernet Controllers
eTSEC1
Offset
0x2_4208 Reserved
0x2_420C TBASE1*—TxBD base address of ring 1
0x2_4210 Reserved
0x2_4214 TBASE2*—TxBD base address of ring 2
0x2_4218 Reserved
0x2_421C TBASE3*—TxBD base address of ring 3
0x2_4220 Reserved
0x2_4224 TBASE4*—TxBD base address of ring 4
0x2_4228 Reserved
0x2_422C TBASE5*—TxBD base address of ring 5
0x2_4230 Reserved
0x2_4234 TBASE6*—TxBD base address of ring 6
0x2_4238 Reserved
0x2_423C TBASE7*—TxBD base address of ring 7
0x2_4240– Reserved
0x2_427C
0x2_4280 TMR_TXTS1_ID* - Tx timestamp identification tag (set 1)
0x2_4284 TMR_TXTS2_ID* - Tx timestamp identification tag (set 2)
0x2_4288– Reserved
0x2_42BC
0x2_42C0 TMR_TXTS1_H* - Tx timestamp high (set 1)
0x2_42C4 TMR_TXTS1_L* - Tx timestamp high (set 1)
0x2_42C8 TMR_TXTS2_H* - Tx timestamp high (set 2)
0x2_42CC TMR_TXTS2_L* - Tx timestamp high (set 2)
0x2_42D0– Reserved
0x2_42FC
0x2_4300 RCTRL—Receive control register
0x2_4304 RSTAT—Receive status register
0x2_4308– Reserved
0x2_430C
0x2_4310 RXIC—Receive interrupt coalescing register
0x2_4314 RQUEUE*—Receive queue control register.
0x2_4318– Reserved
0x2_432C
0x2_4330 RBIFX*—Receive bit field extract control register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-14
Table 15-4. Module Memory Map (continued)
1
Name
eTSEC Receive Control and Status Registers
2
Access Reset
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
w1c 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0080_0080
— —
R/W 0x0000_0000
Freescale Semiconductor
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