Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 88

Overview
interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It
allows data to be locked into the data cache, which may be important to code that must have deterministic
execution.
The e300 core has high-performance 64-bit data bus and 32-bit address bus interfaces to the rest of the
device. The e300 core supports single-beat and burst data transfers for memory accesses, and
memory-mapped I/O operations.
Figure 1-2 provides a block diagram of the e300 core that shows how the execution units (IU1, IU2, FPU,
BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram and
does not attempt to show how these features are physically implemented on the chip.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1-8 Freescale Semiconductor