Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 661

Descriptor field Pointer
Type type Dword1
1000_1 MAC Key
Length
inbound
undefined
tls_ssl_
Extent
block
1010_1
Length
Extent
raid_xor
others
14.4 Execution Units
Execution unit (EU) is the term used for a functional block that performs the mathematical manipulations
required by protocols used in cryptographic processing. The EUs are compatible with IPSec, SSL/TLS,
iSCSI, SRTP, and 802.11i processing, and can work together to perform high level cryptographic tasks.
The following execution units are used in the SEC 2.2:
• Data encryption standard execution unit (DEU) for DES and 3DES as specified by FIPS 46-3
• Advanced encryption standard execution unit (AESU) implementing the Rinjdael symmetric key
cipher per FIPS-197. AESU can perform AES modes CBC, ECB, and CTR modes per NIST SP
800-38A, and CCM mode per NIST SP 800-38C.
• Message digest execution unit (MDEU), implementing MD5 per RFC 1321, and SHA-1,
SHA-224, and SHA-256 per FIPS-180-2. In addition, HMAC is implemented per FIPS 198.
In addition, the two symmetric execution units, DEU and AESU, share their input and output FIFOs.
Working together, the EUs can perform high-level cryptographic tasks, such as IPSec Encapsulating
Security Protocol (ESP). The remainder of this chapter provides details about the execution units
themselves.
14.4.1 Data Encryption Standard Execution Unit (DEU)
This section contains details about the data encryption standard execution unit (DEU), including modes of
operation, status and control registers, and shared symmetric FIFOs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the DEU is used through channel-controlled access,
which means that most reads and writes of DEU registers are directed by the SEC channel. Driver software
would perform host-controlled register accesses only on a few registers for initial configuration and error
handling.
14.4.1.1 DEU Mode Register (DEUMR)
The DEU mode register (DEUMR) contains three bits that are used to program DEU operation.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 14-10. Descriptor Format by Type (continued)
Pointer
Dword2
Cipher IV Cipher Key
undefined undefined
nil nil
nil nil
Pointer Pointer Pointer
Dword 3 Dword4 Dword 5
nil In FIFO
Auth & CIpher
In FIFO MAC In
Auth only
nil ln1 (opt)
nil undefined undefined
Reserved
Security Engine (SEC) 2.2
Pointer
Dword 6
Out FIFO Cipher IV Out
MAC Out
ln2 ln3
undefined
Pointer
Dword 7
undefined
Out
undefined
14-19