Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 980

Universal Serial Bus Interface
for 3 (transactions) × 1024 (maximum packet size) × 8 (transaction records) = 24576 bytes to be moved
with this data structure, regardless of the alignment offset of the first page.
Since each pointer is a 4K-aligned page pointer, the least-significant 12 bits in several of the page pointers
are used for other purposes.
Bits Name
31–12 Buffer Pointer (Page 0) A 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
11–8 EndPt
7 —
6–0 Device Address
Bits Name
31–12 Buffer Pointer This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
(Page 1)
11 I/O Direction (I/O). This field encodes whether the high-speed transaction should use an IN or OUT PID.
0 OUT
1 IN
10–0 Maximum This directly corresponds to the maximum packet size of the associated endpoint ( wMaxPacketSize ).
Packet Size This field is used for high-bandwidth endpoints where more than one transaction is issued per
transaction description (for example, per micro-frame). This field is used with the Multi field to support
high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. Software
should not set a value larger than 1024 (0x400). Any value larger yields undefined results.
Bits Name
31–12 Buffer Pointer
(Page 2)
11–2 —
1–0 Mult
Bits Name
31–12 Buffer Pointer
11–2 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-52
Table 16-42. Buffer Pointer Page 0 (Plus)
Selects the particular endpoint number on the device serving as the data source or sink.
Reserved, should be cleared. Reserved for future use and should be initialized by software
to zero.
This field selects the specific device serving as the data source or sink.
Table 16-43. iTD Buffer Pointer Page 1 (Plus)
Table 16-44. Buffer Pointer Page 2 (Plus)
This is a 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. This bit reserved for future use and should be cleared.
Indicates to the host controller the number of transactions that should be executed per transaction
description (for example, per micro-frame).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
Table 16-45. Buffer Pointer Page 3–6
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. These bits reserved for future use and should be cleared.
Description
Description
Description
Description
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