Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 719

Chapter 15
Enhanced Three-Speed Ethernet Controllers
15.1 Overview
The enhanced three-speed Ethernet controllers (eTSECs) of the device interface to 10 Mbps, 100 Mbps,
and 1 Gbps Ethernet/IEEE 802.3™ networks. For Ethernet, an external PHY or SerDes device is required
to complete the interface to the media. Each eTSEC supports multiple standard media-independent
interfaces. Multiple eTSECs are available, providing flexible options for connectivity and control access
at different speeds.
The eTSEC provides the flexibility to accelerate the identification and retrieval of standard and
non-standard protocols carried over Ethernet, including both IP versions 4 and 6 and TCP/UDP.
CPU-intensive parsing and checksum operations can be optionally off-loaded to an eTSEC to accelerate
existing TCP/IP stacks. On transmission, varying fractions of link bandwidth can be allocated to each of
multiple transmit queues through a modified weighted round-robin scheduler. On receive, an arbitrary set
of queue selection rules can be programmed into each eTSEC to implement flexible quality of service or
firewall strategies based on high-level protocol identification. Without enabling these advanced features,
each eTSEC emulates a PowerQUICC II Pro TSEC, allowing existing driver software to be re-used with
minimal change. Each eTSEC is organized as shown in Figure 15-1.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor 15-1