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Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 652

Integrated
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Security Engine (SEC) 2.2
Address Offset
(AD 17–0)
0x3_4050
AESUEMR—AESU end-of-message register
0x3_4100–0x3_4108 AESU context memory registers
0x3_4400–0x3_4408 AESU key memory registers
0x3_4800–0x3_4FFF AESU FIFO
0x3_6000
MDEUMR—MDEU mode register
0x3_6008
MDEUKSR—MDEU key size register (bytes)
0x3_6010
MDEUDSR—MDEU data size register (bits)
0x3_6018
MDEURCR—MDEU reset control register
0x3_6028
MDEUSR—MDEU status register
0x3_6030
MDEUISR—MDEU interrupt status register
0x3_6038
MDEUICR—MDEU interrupt control register
0x3_6040
MDEU ICV size register
0x3_6050
MDEUEMR—MDEU end-of-message register
0x3_6100–0x3_6120 MDEU context memory registers
0x3_6400–0x3_647F MDEU key memory registers
0x3_6800–0x3_6FFF MDEU FIFO
14.3
Descriptor Overview
The host processor maintains a record of current secure sessions and the corresponding keys and contexts
of those sessions. Once the host has determined that a security operation is required, it creates a
'descriptor' containing all the information the SEC needs to perform the security operation. The host
creates the descriptor in main memory, then writes a pointer to the descriptor into the fetch FIFO of the
SEC channel. The channel uses this pointer to read the descriptor into its descriptor buffer. Once it obtains
the descriptor, the SEC uses its bus mastering capability to obtain inputs and write results, thus off-loading
data movement and encryption operations from the host processor.
For test purposes, it is also possible for the host to write keys, context, and text-data directly to execution
units, using the SEC's host-controlled access. This method avoids use of descriptors.
14.3.1
Descriptor Structure
SEC descriptors are conceptually similar to descriptors used by most devices with DMA capability. The
descriptors have a fixed length of 64 bytes, that is, eight long-words, consisting of one 'header dword' and
seven 'pointer dwords.' See
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-10
Table 14-3. SEC Address Map (continued)
Register
MDEU
Figure 14-3
for the descriptor format.
Access
Access
Section/Page
By
W
Word
14.4.3.8/14-48
R/W
14.4.3.9/14-49
R/W
14.4.3.9.5/14-53
R/W
14.4.3.9.6/14-53
R/W
14.4.2.1/14-28
R/W
14.4.2.3/14-32
R/W
14.4.2.4/14-32
R/W
Word
14.4.2.5/14-33
R
Word
14.4.2.6/14-34
R
Word
14.4.2.7/14-35
R/W
Word
14.4.2.8/14-36
W
14.4.2.9/14-37
W
Word
14.4.2.10/14-38
R/W
14.4.2.11/14-38
W
14.4.2.12/14-39
W
14.4.2.13/14-40
Freescale Semiconductor

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