Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 965

Bits Name
31–19 — Reserved, should be cleared
18–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer.
This bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ETBR[2] (bit 18 of the register) corresponds to endpoint 2.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
15–3 — Reserved, should be cleared
2–0 ERBR Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ERBR[2] corresponds to endpoint 2.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
16.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
Offset 0x2_31BC
31
R
W
Reset
Bits Name
31–19 — Reserved, should be cleared
18–16 ETCE Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software
should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit
is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ETCE[2] (bit 18 of the register) corresponds to endpoint 2.
15–3 — Reserved, should be cleared
2–0 ERCE Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is
set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ERCE[2] corresponds to endpoint 2.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-29. ENDPTSTATUS Register Field Descriptions
21 19 18
—
Figure 16-27. Endpoint Complete (ENDPTCOMPLETE)
Table 16-30. ENDPTCOMPLETE Register Field Descriptions
Description
16 15
ETCE
w1c
All zeros
Description
Universal Serial Bus Interface
Access: w1c
3 2
—
0
ERCE
w1c
16-37