Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 134

Memory Map
Offset
0x3_6038 MDEUICR—MDEU interrupt control register
0x3_6040 MDEU ICV size register
0x3_6050 MDEUEMR—MDEU end-of-message register
0x3_6100– MDEU context memory registers
0x3_6120
0x3_6400– MDEU key memory
0x3_647F
0x3_6800– MDEU FIFO
0x3_6FFF
1
Depends on reset configuration word high values. See
2
Depends on reset configuration word high values. See
for details.
3
Depends on reset configuration word high values. See
details.
4
Depends on reset configuration word high values. See
details.
5
Depends on reset configuration word high values. See
Value," for details.
6
Depends on reset configuration word high values. See
details.
7
Depends on reset configuration word high values. See
Value," for details.
8
Depends on the reset configuration word high configuration values.
9
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
10
Reset value is determined from the core PLL configuration of the reset configuration word. See
and Initialization," for details.
11
The registers AEATR and AEADR are affected only by the assertion of PORESET
12
Implementation-dependent reset values are listed in specified section/page.
13
This register has separate functions for the host and device operation; the host function is listed first in the table.
14
Cleared on read.
15
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-30
Table 2-2. Memory Map (continued)
Register
Section 5.2.4.3.1, "LBLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.4.1, "LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,"
Section 5.2.4.5.1, "PCILAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.7.1, "DDRLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.6.1, "PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset
Section 5.2.4.7.1, "DDRLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.8.1, "DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
Access Reset
R/W 0x0000_0000
_0000_1000
R/W 0x0000_0000_0
000_0000
W 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
W 0x0000_0000
_0000_0000
W 0x0000_0000
_0000_0000
Chapter 4, "Reset, Clocking,
Freescale Semiconductor
Section/Page
14.4.2.8/14-36
14.4.2.9/14-37
14.4.2.10/14-38
14.4.2.11/14-38
14.4.2.12/14-39
14.4.2.13/14-40
for details.
for
for
for