Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 201

4.5.1.4 Reset Mode Register (RMR)
RMR, shown in Figure
checkstop state.
Address 0x0_0914
0
R
W
Reset
16
R
W
Reset
Table 4-29 describes the RMR fields.
Bits Name
0–30 — Reserved, should be cleared.
31 CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception conditions.
Setting CSRE configures the device to perform a hard reset sequence when the core enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
4.5.1.5 Reset Protection Register (RPR)
RPR, shown in Figure
control register (RCR). To disable a write to the reset control register (RCR), the user should write a 1 to
RCER[CRE].
Address 0x0_0918
0
R
W
Reset
16
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
4-9, enables a hard reset sequence on the device when the e300 core enters
Figure 4-9. Reset Mode Register (RMR)
Table 4-29. RMR Field Descriptions
4-10, prevents unintended software reset requests caused by writes to the reset
Figure 4-10. Reset Protection Register (RPR)
—
All zeros
—
All zeros
Function
RCPW
All zeros
RCPW
All zeros
Reset, Clocking, and Initialization
Access: User read/write
30
CSRE
Access: User read/write
15
31
15
31
4-35