Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 632

PCI Bus Interface
Figure 13-49 shows an example of a burst read transaction.
PCI_CLK
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
During the turnaround-cycle following the address phase, the PCI_C/BE[3:0] signals indicate which byte
lanes are involved in the data phase. The turnaround-cycle must be enforced by the target with the
PCI_TRDY signal if using fast PCI_DEVSEL assertion. The earliest the target can provide valid data is
one cycle after the turnaround cycle. The target must drive the AD[31:0] signals when PCI_DEVSEL is
asserted except during the turnaround cycle.
The data phase completes when data is transferred, which occurs when both PCI_IRDY and PCI_TRDY
are asserted on the same clock edge. When either is negated, a wait cycle is inserted and no data is
transferred. To indicate the last data phase PCI_IRDY must be asserted when PCI_FRAME is negated.
A write transaction starts when PCI_FRAME is asserted for the first time and the PCI_C/BE[3:0] signals
indicate a write command.
PCI_CLK
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-50
ADDR DATA1
CMD BYTE ENABLES 1
Figure 13-49. Burst Read Example
Figure 13-50 shows an example of a single-beat write transaction.
ADDR
CMD
Figure 13-50. Single Beat Write Example
DATA2
BYTE ENABLES 2
DATA
BYTE ENABLES
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