Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 173

5. The device samples the reset configuration input signals to determine the clock division and the
reset configuration words source.
6. The device starts loading the reset configuration words.
Loading time depends on the reset configuration word source.
7. When the reset configuration word low is loaded, the system PLL begins to lock.
When the system PLL is locked, csb_clk is supplied to the core PLL.
8. The core PLL begins to lock.
9. The device drives HRESET asserted until the e300 PLL is locked and the reset configuration words
are loaded.
10. The user optionally negates HRESET if it was not negated earlier.
JTAG logic must always be initialized by asserting TRST. If the JTAG signals are not used, TRST
should be connected directly to PORESET. TRST must not remain asserted after the negation of
PORESET. There is no need to assert the SRESET signal when HRESET is asserted.
11. The internal reset to the core and the rest of the logic is negated. I/O drivers are enabled. The PCI
interface can assert DEVSEL in response to configuration cycles.
12. The device stops driving HRESET. The reset to the e300 core is negated and the core is
enabled.The boot sequencer, if enabled, is released, causing it to load configuration data from serial
ROMs, as described in
13. Before the boot sequencer finishes, it can enable the PCI interface to accept external requests, if
required, by clearing the CFG_LOCK bit in the PCI function configuration register as described in
Table 13-40. If the e300 core is required to proceed, the boot sequencer should enable boot vector
fetch by clearing ACR[COREDIS] as described in
(ACR)."
14. The PCI interface can now accept external requests, if enabled, and the boot vector fetch by the
core can proceed, if enabled.
The device is now in its ready state.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Section 17.4.5, "Boot Sequencer Mode."
Reset, Clocking, and Initialization
Section 6.2.1, "Arbiter Configuration Register
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