Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 112

Memory Map
Offset
0x1C System internal interrupt group D priority register
(SIPRR_D)
0x20 System internal interrupt mask register (SIMSR_H)
0x24 System internal interrupt mask register (SIMSR_L)
0x28 System internal interrupt control register (SICNR)
0x2C System external interrupt pending register (SEPNR)
0x30 System mixed interrupt group A priority register
(SMPRR_A)
0x34 System mixed interrupt group B priority register
(SMPRR_B)
0x38 System external interrupt mask register (SEMSR)
0x3C System external interrupt control register (SECNR)
0x40 System error status register (SERSR)
0x44 System error mask register (SERMR)
0x48 System error control register (SERCR)
0x4C–0x4F Reserved
0x50 System internal interrupt force register (SIFCR_H)
0x54 System internal interrupt force register (SIFCR_L)
0x58 System external interrupt force register (SEFCR)
0x5C System error force register (SERFR)
0x60 System critical interrupt vector register (SCVCR)
0x64 System management interrupt vector register (SMVCR)
0x68–0xFF Reserved
0x00 Arbiter configuration register (ACR)
0x04 Arbiter timers register (ATR)
0x0C Arbiter event register (AER)
0x10 Arbiter interrupt definition register (AIDR)
0x14 Arbiter mask register (AMR)
0x18 Arbiter event attributes register (AEATR)
0x1C Arbiter event address register (AEADR)
0x20 Arbiter event response register (AERR)
0x0_0900 Reset configuration word low register (RCWLR)
0x0_0904 Reset configuration word high register (RCWHR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-8
Table 2-2. Memory Map (continued)
Register
System Arbiter Registers
Reset Module
Access Reset
R/W 0x0530_9770
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W Special
R/W 0x0530_9770
R/W 0x0530_9770
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R 0x0000_0000
— —
R/W 0x0000_0000/
10
0x0010_0000
R/W 0xFFFF_FFFF
w1c 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
11
R 0x0000_0000
11
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R 0x0000_0000
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