Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 560

Sequencer
Figure 11-7 shows an example translation window for outbound memory accesses.
0
PCI Memory/IO Space
PCI Outbound
Translation
Address
Outbound
Memory
Window Size
4G
The six sets of outbound translation registers allow six simultaneous translation windows to the PCI port.
Software can move and adjust the memory window translations and sizes during run-time. This allows
software to access different PCI memory/IO spaces on-the-fly, but the PCI outbound translation source
windows must not overlap. However, outbound translation destination windows can be overlapped.
11.5.3 Transaction Ordering
The following rules are applied to maintain proper ordering of transactions:
• The transactions arriving from each port are dispatched to the destination port in the order of
arrival. The dispatch order of transactions arriving on different ports is not necessarily maintained.
• A read transaction that originates at the CSB port and reads from the PCI port pulls out of the IOS
any posted writes that originated on the PCI port and were posted before the read data arrives from
the PCI.
• The IOS can always accept a write from the PCI port without forcing the PCI port to first accept a
read.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
11-8
PCI Memory View
System Memory
Destination Window
Outbound Address
PCI Memory
Figure 11-7. Outbound PCI Memory Address Translation
CSB View
0
Local Memory
Translation
PCI Memory
Outbound Memory
Source Window
4G
PCI Outbound
Base
Address
Outbound
Memory
Window Size
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