Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 863

4. Clearing DMACTRL[GTS] triggers the transmission of frame data if the transmitter had been
previously stopped. The DMACTRL[GRS] must be cleared if the receiver had been previously
stopped. Refer to the DMACTRL register section, and
Descriptors," for more information.
15.6.2.2 Soft Reset and Reconfiguring Procedure
Before issuing a soft-reset to and/or reconfiguring the MAC with new parameters, the user must properly
shutdown the DMA and make sure it is in an idle state for the entire duration. User must gracefully stop
the DMA by setting both GRS and GTS bits in the DMACTRL register, then wait for both GRSC and
GTSC bits to be set in the IEVENT register before resetting the MAC or changing parameters. Both GRS
and GTS bits must be cleared before re-enabling the MAC to resume the DMA.
During the MAC configuration, if a new set of Tx buffer descriptors are used, the user must load the
pointers into the TBASE registers. Likewise if a new set of Rx buffer descriptors are used, the RBASE
registers must be written with new pointers.
Following is a procedure to gracefully reset and reconfigure the MAC:
1. Set GRS/GTS bits in DMACTRL register
2. Poll GRSC/GTSC bits in IEVENT register until both are set
3. Set SOFT_RESET bit in MACCFG1 register (Note that SOFT_RESET must remain set for at least
3 TX clocks before proceeding.)
4. Clear SOFT_RESET bit in MACCFG1 register
5. Load TBASE0–TBASE7 with new Tx BD pointers
6. Load RBASE0–RBASE7 with new Rx BD pointers
7. Setup other MAC registers (MACCFG2, MAXFRM, and so on)
8. Setup group address hash table (GADDR0–GADDR15) if address filtering is required
9. Setup receive frame filer table (through RQFAR, RQFCR, and RQFPR) if filing to multiple RxBD
rings is required
10. Setup WWR, WOP, TOD bits in DMACTRL register
11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set
in TCTRL.
12. Enable receive queues in RQUEUE, and optionally set TOE functionality in RCTRL.
13. Clear THLT and TXF bits in TSTAT register by writing 1 to them
14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.
15. Clear GRS/GTS bits in DMACTRL (do not change other bits)
16. Enable Tx_EN/Rx_EN in MACCFG1 register
15.6.2.3 Gigabit Ethernet Frame Transmission
The Ethernet transmitter requires little core intervention. After the software driver initializes the system,
the eTSEC begins to poll the first transmit buffer descriptor (TxBD) in TxBD ring 0 every 512 transmit
clocks. If TxBD[R] is set, and the TxBD ring is scheduled for transmission, the eTSEC begins copying the
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Enhanced Three-Speed Ethernet Controllers
Section 15.6.7.1, "Data Buffer
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