Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 671

0
Field
Reset
R/W
Addr
Figure 14-15. MDEU Mode Register (MDEUMR) in 'Old' Configuration
Table 14-17 describes MDEUMR fields in 'old' configuration.
Bits Name
The following bits are described for information only. They are not under direct user control.
0–53 — Reserved
54 NEW=0 Determines the configuration of the MDEU mode register (MDEUMR). This table shows the configuration
for NEW = 0.
55 — Reserved, must be set to zero
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
56 CONT Continue. Most operations will require this bit to be cleared. It is set only when the data to be hashed is
spread across multiple descriptors.
The value programmed in PD must be opposite to the value in this bit.
0 Do autopadding and complete the message digest. Used when the entire hash is performed with one
descriptor, or on the last of a sequence of descriptors.
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the
message digest.
57 CICV Compare integrity check values
0 Normal operation; no ICV comparison
1 After the message digest (ICV) is computed, compare it to the data in the MDEU's input FIFO. If the ICVs
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by
the ICV size register.
Only applicable to descriptor types that provide for reading an ICV in value.
58 SMAC Specifies whether to perform an SSL-MAC operation
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then the HMAC bit
should be 0.
59 INIT Initialization bit. Most operations will require this bit to be set. Cleared only for operations that load context
from a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash context pointer in
the descriptor. When the data to be hashed is spread across multiple descriptors, this bit must be 0 on
all but the first descriptor.
1 Do an algorithm-specific initialization of the digest registers.
60 HMAC Specifies whether to perform an HMAC operation
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should
be 0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
53
— NEW=0
MDEU 0x3_6000
Table 14-17. MDEUMR in 'Old' Configuration
54 55 56 57
— CONT CICV SMAC INIT HMAC PD
0
R/W
Description
Security Engine (SEC) 2.2
58 59 60 61 62 63
ALG
14-29