Freescale Semiconductor MPC8313 PowerQUICC II Pro Manuals

Manuals and User Guides for Freescale Semiconductor MPC8313 PowerQUICC II Pro. We have 2 Freescale Semiconductor MPC8313 PowerQUICC II Pro manuals available for free PDF download: Family Reference Manual

Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual

Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual (1250 pages)

PowerQUICC II Pro Integrated Processor

Brand: Freescale Semiconductor | Category: Processor | Size: 9.81 MB

Table of Contents

Table of Contents

3
Figures

57
- Number Title Number
  74
  - About this Book
    75
  - General Information
    77
  - Related Documentation
    78
- Acronyms and Abbreviated Terms
  79
- Mpc8313E Powerquicc II Pro Processor Overview
  83
- Chapter 1
  
  89
  - Mpc8313E Architecture Overview
    89
  - Power Architecture Core
    89
- Chapter 14 Security Engine
  
  92
- Chapter 9
  
  92
- Chapter 8 Integrated Programmable Interrupt Controller (Ipic)
  
  98
  - Dma Controller
    99
  - Application Examples
    100
    
    Low-End Printer Cpu and Interface Asic
    101
    
    High-End Printer I/O Processor
    102
    
    Ieee Std. 1588 in Test and Measurement and Industrial Automation
    103
    
    Ieee Std. 802.11N Wlan Access Point
    105
    
    Media Server
    106
  - Serial Peripheral Interface (Spi)
    100
  - System Timers
    100
  - Accessing Immr Memory from the Local Processor
    107
  - Complete Immr Map
    107
  - Internal Memory Mapped Registers
    107
  - IMMR Memory Map
    108
  - Memory Map
    110
- Chapter 2 Signal Descriptions
  
  141
  - Mpc8313E Powerquicc II Pro Integrated Processor Family Reference Manual, Rev
    141
  - MPC8313E Signal Reference by Functional Block
    142
  - System Control Signals
    142
  - Table Page
    142
  - Reset Configuration Signals
    167
  - Output Signal States During System Reset
    168
  - Signals for Multiplexing
    169
  - External Signals-Detailed Signal Descriptions
    170
    
    External Signals
    171
  - External Clock Signals
    173
  - Functional Description
    174
  - Reset Actions
    175
- Chapter 4
  
  176
  - Reset Causes
    175
  - Power-On Reset Flow
    176
  - Hard Reset Flow
    178
  - Reset Configuration
    179
  - Reset Configuration Signals
    179
  - Soft Reset Flow
    179
  - Reset Configuration Words Source
    180
    
    Sys_Clk_In Division
    181
  - Selecting Reset Configuration Input Signals
    181
    
    Reset Configuration Words
    182
    
    SPMF Maximum Values
    184
    
    System Pll Configuration
    184
    
    System PLL Ratio
    184
  - Boot Sequencer Configuration
    186
    
    Boot Memory Space (Bms)
    187
    
    Boot Sequencer Configuration
    187
  - PCI Host/Agent Configuration
    186
  - Boot ROM Location
    188
  - Etsec1 Mode Configuration
    189
  - Etsec2 Mode Configuration
    190
    
    E300 Core True Little Endian
    191
    
    LALE Configuration
    191
    
    Loading from Local Bus
    191
    
    Loading the Reset Configuration Words
    191
    
    Local Bus Configuration EEPROM Addresses
    192
    
    Local Bus Controller Setting
    192
    
    Local Bus Reset Configuration Words Data Structure
    192
    
    Local Bus Controller Setting When Loading RCW
    193
    
    Using the Boot Sequencer Reset Configuration
    193
    
    Eeprom Data Format in Reset Configuration Mode
    194
    
    Default Reset Configuration Words
    196
    
    Hard Coded Reset Configuration Word Low Fields Values
    196
    
    Reset Configuration Load Fail
    196
  - Examples for Hard-Coded Reset Configuration Words Usage
    197
    
    Clocking in Pci Agent Mode
    200
    
    Clocking in Pci Host Mode
    200
    
    System Clock Domains
    200
    
    Configurable Clock Units
    201
    
    Usb Clocking
    201
    
    Ethernet Clocking
    202
    
    Real-Time Clock (Rtc)
    202
    
    Reset Configuration and Status Registers Memory Map
    202
    
    Reset Configuration Register Descriptions
    202
    
    Reset Status Register (Rsr)
    203
    
    Reset Mode Register (Rmr)
    204
    
    Reset Control Register (Rcr)
    205
    
    Reset Protection Register (Rpr)
    205
    
    RMR Field Descriptions
    205
    
    Clock Configuration Registers Memory Map
    206
    
    Reset Control Enable Register (Rcer)
    206
    
    System Pll Mode Register (Spmr)
    207
    
    Output Clock Control Register (Occr)
    208
    
    System Clock Control Register (Sccr)
    209
    
    Local Access Windows Target Interface
    211
- Chapter 5
  
  211
  - Hard-Coded Reset Configuration Word High Field Values
    197
  - Local Memory Map Overview and Example
    211
  - Local Access Windows Example
    212
    
    Format of Window Definitions
    213
  - Address Translation and Mapping
    213
  - Local Access Windows
    214
    
    Local Access Register Memory Map
    214
  - Window into Configuration Space
    214
  - Local Access Register Descriptions
    216
    
    Internal Memory Map Registers Base Address Register (Immrbar)
    216
    
    Updating Immrbar
    216
    
    ALTCBAR Bit Settings
    217
    
    Alternate Configuration Base Address Register (Altcbar)
    217
    
    IMMRBAR Bit Settings
    217
    
    Lbc Local Access Window N Base Address Registers
    218
    
    LBLAWBAR0-LBLAWBAR3 Bit Settings
    218
    
    LBLAWBAR0[BASE_ADDR] Reset Value
    218
  - LBLAWAR0-LBLAWAR3 Bit Settings
    219
  - LBLAWAR0[EN] Reset Value
    219
    
    Pci Local Access Window N Base Address Register
    220
    
    PCILAWBAR0-PCILAWBAR1 Bit Settings
    220
    
    PCILAWBAR0[BASE_ADDR] Reset Value
    220
    
    Pci Local Access Window N Attributes Registers
    221
    
    PCILAWAR0-PCILAWAR1 Bit Settings
    221
    
    Pcilawar0[En] and Pcilawar0[Size] Reset Value
    221
    
    PCILAWAR0[EN] Reset Value
    221
    
    Ddr Local Access Window N Base Address Registers
    222
    
    DDRLAWBAR0-DDRLAWBAR1 Bit Settings
    222
    
    DDRLAWBAR0[BASE_ADDR] Reset Value
    222
    
    Ddr Local Access Window N Attributes Registers
    223
    
    DDRLAWAR0-DDRLAWAR1 Bit Settings
    223
    
    Ddrlawar0[En] and Ddrlawar0[Size] Reset Value
    223
    
    DDRLAWAR0[EN] Reset Value
    224
    
    Overlapping Local Access Windows
    224
  - Configuring Local Access Windows
    224
  - Precedence of Local Access Windows
    224
  - Inbound Address Translation and Mapping Windows
    225
    
    Pci Inbound Windows
    225
  - Internal Memory Map
    225
  - Outbound Address Translation and Mapping Windows
    225
  - Accessing Internal Memory from External Masters
    226
    
    System Configuration Register Memory Map
    226
    
    SGPRH Bit Settings
    227
    
    SGPRL Bit Settings
    227
  - System Configuration Registers
    227
    
    System General Purpose Register High (Sgprh)
    227
    
    System General Purpose Register Low (Sgprl)
    227
    
    PARTID Coding
    228
    
    REVID Coding
    228
    
    SPRIDR Bit Settings
    228
    
    Spridr[Partid] Coding
    228
    
    System Part and Revision ID Register (Spridr)
    228
    
    System Priority and Configuration Register (Spcr)
    228
  - SPCR Bit Settings
    229
    
    SICRL Bit Settings
    231
    
    System I/O Configuration Register Low (Sicrl)
    231
    
    System I/O Configuration Register High (Sicrh)
    233
  - SICRH Bit Settings
    234
    
    Debug Configuration
    236
    
    SICRH[30-31] Bit Settings
    236
    
    Ddr Control Driver Register (Ddrcdr)
    237
    
    Ddr Debug Configuration
    237
    
    DDRCDR Field Descriptions
    237
    
    Local Bus Debug Configuration
    237
    
    Ddr Debug Status Register (Ddrdsr)
    238
    
    DDRDSR Field Descriptions
    239
  - Software Watchdog Timer (Wdt)
    239
    
    Wdt Overview
    239
    
    Wdt Features
    240
    
    Wdt Modes of Operation
    240
    
    System Watchdog Control Register (Swcrr)
    241
    
    Wdt Memory Map/Register Definition
    241
    
    WDT Register Address Map
    241
    
    SWCRR Bit Settings
    242
    
    System Watchdog Count Register (Swcnr)
    242
    
    SWCNR Bit Settings
    243
    
    System Watchdog Service Register (Swsrr)
    243
    
    Software Watchdog Timer Unit
    244
    
    Modes of Operation
    245
    
    Rtc External Signal Description
    247
    
    Rtc Features
    247
    
    Rtc Modes of Operation
    247
    
    Real Time Counter Control Register (Rtcnr)
    248
    
    Rtc Memory Map/Register Definition
    248
    
    Real Time Counter Load Register (Rtldr)
    249
    
    Real Time Counter Prescale Register (Rtpsr)
    250
    
    Real Time Counter Register (Rtctr)
    250
    
    Real Time Counter Alarm Register (Rtalr)
    251
    
    Real Time Counter Event Register (Rtevr)
    251
    
    Real Time Counter Unit
    252
    
    Rtc Operational Modes
    252
    
    Rtc Programming Guidelines
    253
  - Periodic Interval Timer (Pit)
    253
    
    Pit Features
    254
    
    Pit Modes of Operation
    254
    
    Pit Overview
    254
    
    Pit External Signal Description
    255
    
    Pit Memory Map/Register Definition
    255
    
    Periodic Interval Timer Control Register (Ptcnr)
    256
    
    Periodic Interval Timer Load Register (Ptldr)
    256
    
    Periodic Interval Timer Counter Register (Ptctr)
    257
    
    Periodic Interval Timer Prescale Register (Ptpsr)
    257
    
    Periodic Interval Timer Event Register (Ptevr)
    258
    
    Periodic Interval Timer Unit
    258
    
    Pit Operational Modes
    259
    
    Pit Programming Guidelines
    259
  - General-Purpose Timers (Gtms)
    260
    
    Gtm Overview
    260
    
    Gtm Features
    261
    
    Gtm Modes of Operation
    261
    
    Clock Source Modes
    262
    
    Gtm External Signal Description
    262
    
    Gtm Memory Map/Register Definition
    264
    
    Global Timers Mode Registers (Gtmdr1–Gtmdr)
    268
    
    Global Timers Capture Registers (Gtcpr1–Gtcpr)
    270
    
    Global Timers Counter Registers (Gtcnr1–Gtcnr)
    270
    
    Global Timers Reference Registers (Gtrfr1–Gtrfr)
    270
    
    Global Timers Event Registers (Gtevr1–Gtevr)
    271
    
    Global Timers Prescale Registers (Gtpsr1–Gtpsr)
    272
    
    General-Purpose Timer Units
    273
    
    Gtm Registers
    276
    
    Programming Guidelines
    276
  - Power Management Control (Pmc)
    276
    
    Pmc Memory Map/Register Definition
    277
    
    Power Management Controller Configuration Register (Pmccr)
    278
    
    Power Management Controller Event Register (Pmcer)
    278
    
    Power Management Controller Mask Register (Pmcmr)
    280
    
    Power Management Controller Configuration Register 1 (Pmccr)
    281
    
    Power Management Controller Configuration Register 2 (Pmccr)
    283
    
    Dynamic Power Management
    284
    
    Shutting down Unused Blocks
    285
    
    Software-Controlled Power Supply Switching
    285
    
    Software-Controlled Power-Down States
    285
    
    Support of Pci Power Management Interface Specification
    286
    
    Entering Low Power States—Core and System Mode
    289
    
    Entering Low Power States—Core-Only Mode
    289
    
    Exiting Core and System Low Power States
    290
    
    Exiting Low Power States—Core and System Mode
    290
    
    Exiting Low Power States—Core-Only Mode
    290
    
    Mpc8313E-Specific Pmc Low Power States
    291
    
    Power State Transitions from an Acpi Perspective
    291
    
    Mpc8313E Low Power Sequencing
    295
    
    Pmc External Power Supply Control
    300
    
    Low-Power Considerations
    302
    
    Core Disable in Low Power Mode
    303
  - Arbiter Overview
    305
- Chapter 6 Coherent System Bus Overview
  
  305
  - Arbiter Memory Map/Register Definition
    306
    
    Arbiter Configuration Register (Acr)
    306
    
    Arbiter Timers Register (Atr)
    308
    
    Arbiter Event Register (Aer)
    310
    
    Arbiter Interrupt Definition Register (Aidr)
    311
    
    Arbiter Mask Register (Amr)
    312
    
    Arbiter Event Attributes Register (Aeatr)
    313
    
    Arbiter Event Address Register (Aeadr)
    314
    
    Arbiter Event Response Register (Aerr)
    315
    
    Arbitration Policy
    316
    
    Address Bus Arbitration with Repeat
    317
    
    Address Bus Arbitration after Artry
    318
    
    Address Bus Parking
    318
    
    Bus Error Detection
    318
    
    Data Bus Arbitration
    318
    
    Address Only Transaction Type
    319
    
    Address Time out
    319
    
    Data Time out
    319
    
    Transfer Error
    319
    
    Reserved Transaction Type
    320
  - Initialization/Applications Information
    321
    
    Error Handling Sequence
    321
  - E300C3 Overview
    323
- Chapter 7
  
  325
  - E300C3 Features
    325
  - Instruction Unit
    328
    
    Instruction Queue and Dispatch Unit
    328
    
    Branch Processing Unit (Bpu)
    329
  - Independent Execution Units
    329
    
    Floating-Point Unit (Fpu)
    329
    
    Integer Unit (Iu)
    329
    
    Load/Store Unit (Lsu)
    330
    
    System Register Unit (Sru)
    330
  - Completion Unit
    330
  - Memory Subsystem Support
    330
    
    Memory Management Units (Mmus)
    331
    
    Bus Interface Unit (Biu)
    332
    
    Cache Units
    332
  - Power Management
    333
    
    Time Base/Decrementer
    333
    
    Clock Multiplier
    334
    
    Core Performance Monitor
    334
    
    Jtag Test and Debug Interface
    334
  - System Support Functions
    333
  - Implementation-Specific Information
    335
    
    Register Model
    336
    
    Condition Register (Cr)
    338
    
    Floating-Point Registers (Fprs)
    338
    
    Floating-Point Status and Control Register (Fpscr)
    338
    
    General-Purpose Registers (Gprs)
    338
    
    Uisa Registers
    338
    
    User-Level Sprs
    338
    
    Machine State Register (Msr)
    339
    
    Oea Registers
    339
    
    Vea Registers
    339
    
    Segment Registers (Srs)
    341
    
    Supervisor-Level Sprs
    341
    
    Instruction Set and Addressing Modes
    348
    
    Powerpc Instruction Set and Addressing Modes
    348
    
    Implementation-Specific Instruction Set
    349
    
    Cache Implementation
    350
    
    Implementation-Specific Cache Organization
    350
    
    Powerpc Cache Characteristics
    350
    
    Instruction and Data Cache Way-Locking
    352
    
    Interrupt Model
    352
    
    Powerpc Interrupt Model
    352
    
    Implementation-Specific Interrupt Model
    353
    
    Implementation-Specific Memory Management
    356
    
    Memory Management
    356
    
    Powerpc Memory Management
    356
    
    Instruction Timing
    357
    
    Core Interface
    358
    
    Memory Accesses
    359
    
    Breakpoint Signaling
    360
    
    Debug Features
    360
  - Powerpc Architecture Implementation
    335
  - Differences between Cores
    361
  - Ipic Introduction
    363
  - Ipic Features
    366
  - Ipipc Modes of Operation
    366
    
    Core Enable Mode
    366
    
    Core Disable Mode
    367
  - Ipic External Signal Description
    367
    
    Ipic Detailed Signal Descriptions
    367
    
    Ipic External Signals Overview
    367
  - Ipic Memory Map/Register Definition
    368
    
    System Global Interrupt Configuration Register (Sicfr)
    369
    
    System Global Interrupt Vector Register (Sivcr)
    371
    
    System Internal Interrupt Group a Priority Register (Siprr_A)
    375
    
    System Internal Interrupt Group D Priority Register (Siprr_D)
    376
    
    System Internal Interrupt Mask Register (Simsr_H and Simsr_L)
    377
    
    System Internal Interrupt Control Register (Sicnr)
    378
    
    System External Interrupt Pending Register (Sepnr)
    380
    
    System Mixed Interrupt Group a Priority Register (Smprr_A)
    380
    
    System Mixed Interrupt Group B Priority Register (Smprr_B)
    381
    
    System External Interrupt Mask Register (Semsr)
    382
    
    System External Interrupt Control Register (Secnr)
    383
    
    System Error Status Register (Sersr)
    384
    
    System Error Mask Register (Sermr)
    385
    
    System Error Control Register (Sercr)
    386
    
    System Internal Interrupt Force Registers (Sifcr_H and Sifcr_L)
    387
    
    System Error Force Register (Serfr)
    388
    
    System External Interrupt Force Register (Sefcr)
    388
    
    System Critical Interrupt Vector Register (Scvcr)
    389
    
    System Management Interrupt Vector Register (Smvcr)
    389
    
    Interrupt Types
    390
    
    Interrupt Configuration
    391
    
    Internal Interrupts Group Relative Priority
    392
    
    Mixed Interrupts Group Relative Priority
    392
    
    Highest Priority Interrupt
    393
    
    Interrupt Source Priorities
    393
    
    Masking Interrupt Sources
    396
    
    Interrupt Vector Generation and Calculation
    397
    
    Machine Check Interrupts
    397
    
    Clock Interface Signals
    405
    
    Debug Signals
    406
    
    Register Descriptions
    407
    
    Ddr Sdram Control Configuration (Ddr_Sdram_Cfg)
    416
    
    Ddr Sdram Mode Configuration (Ddr_Sdram_Mode)
    420
    
    Ddr Sdram Mode Control Register (Ddr_Sdram_Md_Cntl)
    422
    
    Ddr Sdram Data Initialization (Ddr_Data_Init)
    425
    
    Ddr Sdram Interval Configuration (Ddr_Sdram_Interval)
    425
    
    Ddr Initialization Address (Ddr_Init_Addr)
    426
    
    Ddr Sdram Clock Control (Ddr_Sdram_Clk_Cntl)
    426
    
    Ddr Ip Block Revision 1 (Ddr_Ip_Rev)
    427
    
    Ddr Ip Block Revision 2 (Ddr_Ip_Rev)
    427
    
    Ddr Sdram Interface Operation
    431
    
    Supported Ddr Sdram Organizations
    432
    
    Ddr Sdram Address Multiplexing
    433
    
    Jedec Standard Ddr Sdram Interface Commands
    438
    
    Ddr Sdram Interface Timing
    439
    
    Clock Distribution
    443
    
    Ddr Sdram Mode-Set Command Timing
    443
    
    Ddr Sdram Registered DIMM Mode
    444
    
    Ddr Sdram Write Timing Adjustments
    444
    
    Ddr Sdram Refresh
    445
    
    Ddr Sdram Refresh and Power-Saving Modes
    446
    
    Ddr Sdram Refresh Timing
    446
    
    Ddr Data Beat Ordering
    448
    
    Self-Refresh in Sleep Mode
    448
    
    Page Mode and Logical Bank Retention
    449
    
    Programming Differences between Memory Types
    451
  - Ddr Sdram Initialization Sequence
    453
- Chapter 10
  
  457
  - Elbc Bus Clock and Clock Ratios
    457
  - Source ID Debug Mode
    458
    
    Option Registers (Or0–Or)
    465
    
    Address Mask
    466
  - Upm Memory Address Register (Mar)
    473
  - Memory Refresh Timer Prescaler Register (Mrtpr)
    476
  - Upm/Fcm Data Register (Mdr)
    476
  - Special Operation Initiation Register (Lsor)
    477
  - Upm Refresh Timer (Lurt)
    478
  - Transfer Error Status Register (Ltesr)
    479
  - Transfer Error Check Disable Register (Ltedr)
    481
  - Transfer Error Interrupt Enable Register (Lteir)
    482
  - Transfer Error Attributes Register (Lteatr)
    483
  - Transfer Error Address Register (Ltear)
    484
  - Local Bus Configuration Register (Lbcr)
    485
  - Transfer Error Ecc Register (Lteccr)
    485
  - Clock Ratio Register (Lcrr)
    487
  - Flash Mode Register (Fmr)
    488
  - Flash Instruction Register (Fir)
    489
  - Flash Command Register (Fcr)
    490
  - Flash Block Address Register (Fbar)
    491
  - Flash Page Address Register (Fpar)
    491
  - Flash Byte Count Register (Fbcr)
    493
  - Basic Architecture
    495
    
    Address and Address Space Checking
    495
    
    External Address Latch Enable Signal (Lale)
    496
    
    Data Transfer Acknowledge (Ta)
    497
    
    Atomic Operation
    498
    
    Data Buffer Control (Lbctl)
    498
    
    Bus Monitor
    499
  - General-Purpose Chip-Select Machine (Gpcm)
    499
    
    Gpcm Read Signal Timing
    500
    
    Gpcm Write Signal Timing
    502
    
    Chip-Select Assertion Timing
    504
    
    Chip-Select and Write Enable Negation Timing
    505
    
    Programmable Wait State Configuration
    505
    
    Relaxed Timing
    506
    
    Output Enable (Loe) Timing
    509
    
    External Access Termination (Lgta)
    510
    
    Gpcm Boot Chip-Select Operation
    511
  - Flash Control Machine (Fcm)
    512
    
    Fcm Buffer Ram
    514
    
    Buffer Layout and Page Mapping for Small-Page Nand Flash Devices
    515
    
    Buffer Layout and Page Mapping for Large-Page Nand Flash Devices
    516
    
    Error Correcting Codes and the Spare Region
    517
    
    Programming Fcm
    518
    
    Fcm Command Instructions
    519
    
    Fcm Address Instructions
    520
    
    Fcm Data Read Instructions
    520
    
    Fcm No-Operation Instruction
    520
    
    Fcm Chip-Select Timing
    521
    
    Fcm Data Write Instructions
    521
    
    Fcm Signal Timing
    521
    
    Fcm Command, Address, and Write Data Timing
    522
    
    Fcm Ready/Busy Timing
    523
    
    Fcm Read Data Timing
    524
    
    Fcm Boot Chip-Select Operation
    525
    
    Fcm Extended Read Hold Timing
    525
    
    Boot Block Loading into the Fcm Buffer Ram
    526
    
    Fcm Bank 0 Reset Initialization
    526
  - User-Programmable Machines (Upms)
    528
    
    Upm Requests
    529
    
    Memory Access Requests
    530
    
    Upm Refresh Timer Requests
    530
    
    Exception Requests
    531
    
    Programming the Upms
    531
    
    Software Requests—Run Command
    531
    
    Upm Programming Example (Two Sequential Writes to the Ram Array)
    532
    
    Upm Programming Example (Two Sequential Reads from the Ram Array)
    533
    
    Upm Signal Timing
    533
    
    Ram Array
    534
    
    Ram Words
    534
    
    Loop Control (Loop)
    540
    
    Address Multiplexing (Amx)
    541
    
    Repeat Execution of Current Ram Word (Redo)
    541
    
    Data Valid and Data Sample Control (Uta)
    543
    
    Lgpl[0:5] Signal Negation (Last)
    543
    
    Wait Mechanism (Waen)
    543
  - Interfacing to Peripherals in Different Address Modes
    545
    
    Multiplexed Address/Data Bus for 26-Bit Addressing
    545
    
    Non-Multiplexed Address and Data Buses
    545
    
    Peripheral Hierarchy on the Local Bus for High Bus Speeds
    546
    
    Gpcm Timings
    547
  - Bus Turnaround
    547
    
    Address Phase after Previous Read
    548
    
    Read Data Phase after Address Phase
    548
    
    Read-Modify-Write Cycle for Parity Protected Memory Banks
    548
    
    Upm Cycles with Additional Address Phases
    548
  - Interface to Different Port-Size Devices
    548
  - Command Sequence Examples for Nand Flash Eeprom
    550
    
    Nand Flash Soft Reset Command Sequence Example
    550
    
    Nand Flash Read Identification Command Sequence Example
    551
    
    Nand Flash Read Status Command Sequence Example
    551
    
    Nand Flash Block Erase Command Sequence Example
    552
    
    Nand Flash Page Read Command Sequence Example
    552
    
    Nand Flash Program Command Sequence Example
    553
  - Interfacing to Fast-Page Mode Dram Using Upm
    554
  - Interfacing to Zbt Sram Using Upm
    559
  - Sequencer Overview
    563
- Chapter 11 Sequencer
  
  564
  - Sequencer External Signal Description
    564
  - Sequencer Features
    564
  - Sequencer Memory Map/Register Definition
    564
  - Sequencer Register Descriptions
    565
    
    Power Management Control Register (Pmcr)
    567
    
    Discard Timer Control Register (Dtcr)
    568
    
    Transaction Forwarding
    568
    
    Pci Outbound Address Translation
    569
    
    Transactions from the Coherency System Bus (Csb) Port
    569
    
    Transactions from the Dma Port
    569
    
    Transactions from the Pci Port
    569
    
    Transaction Ordering
    570
- Chapter 12
  
  571
  - Dma Features
    571
  - Dma Memory Map/Register Definition
    572
  - Dma Register Descriptions
    573
    
    Outbound Message Interrupt Status Register (Omisr)
    573
    
    Outbound Message Interrupt Mask Register (Omimr)
    574
    
    Inbound Message Registers (Imr0–Imr)
    575
    
    Outbound Message Registers (Omr0–Omr)
    575
    
    Doorbell Registers
    576
    
    Outbound Doorbell Register (Odr)
    576
    
    Inbound Doorbell Register (Idr)
    577
    
    Inbound Message Interrupt Status Register (Imisr)
    577
    
    Inbound Message Interrupt Mask Register (Imimr)
    578
    
    Dma Registers
    579
    
    Dma General Status Register (Dmagsr)
    585
    
    Message Unit
    585
    
    Messaging Registers (Imr0–Imr1, Omr0–Omr)
    585
    
    Dma Operation
    586
    
    Doorbell Registers (Idr and Odr)
    586
    
    Dma Coherency
    587
    
    Dma Segment Descriptors
    588
    
    Halt and Error Conditions
    588
    
    Descriptor in Big-Endian Mode
    589
    
    Descriptor in Little-Endian Mode
    590
    
    Initialization Steps in Direct Mode
    590
    
    Initialization Steps in Chaining Mode
    591
  - Pci Introduction
    593
- Chapter 13
  
  595
  - Pci Features
    595
  - Pci Modes of Operation
    595
    
    Host/Agent Mode Configuration
    595
    
    Pci Arbiter Configuration
    596
  - Pci External Signal Description
    596
  - Pci Memory Map/Register Definitions
    603
    
    Pci Configuration Access Registers
    605
    
    Pci Error Status Register (Pci_Esr)
    607
    
    Pci Interrupt Acknowledge Register (Pci_Int_Ack)
    607
    
    Pci Memory-Mapped Control and Status Registers
    607
    
    Pci Error Capture Disable Register (Pci_Ecdr)
    608
    
    Pci Error Enable Register (Pci_Eer)
    609
    
    Pci Error Attributes Capture Register (Pci_Eatcr)
    610
    
    Pci Error Address Capture Register (Pci_Eacr)
    611
    
    Pci Error Data Low Capture Register (Pci_Edlcr)
    612
    
    Pci Error Extended Address Capture Register (Pci_Eeacr)
    612
    
    Pci General Control Register (Pci_Gcr)
    612
    
    Pci Error Control Register (Pci_Ecr)
    613
    
    Pci General Status Register (Pci_Gsr)
    614
  - Pci Configuration Space Registers
    617
    
    Device ID Configuration Register
    619
    
    Vendor ID Configuration Register
    619
    
    Pci Command Configuration Register
    620
    
    Pci Status Configuration Register
    621
    
    Revision ID Configuration Register
    622
    
    Standard Programming Interface Configuration Register
    622
    
    Base Class Code Configuration Register
    623
    
    Subclass Code Configuration Register
    623
    
    Cache Line Size Configuration Register
    624
    
    Latency Timer Configuration Register
    624
    
    Bist Control Configuration Register
    625
    
    Header Type Configuration Register
    625
    
    Pimmr Base Address Configuration Register
    625
    
    Gpl Base Address Register
    626
    
    Capabilities Pointer Configuration Register
    628
    
    Subsystem Device ID Configuration Register
    628
    
    Subsystem Vendor ID Configuration Register
    628
    
    Interrupt Line Configuration Register
    629
    
    Interrupt Pin Configuration Register
    629
    
    Minimum Grant Configuration Register
    629
    
    Maximum Latency Configuration Register
    630
    
    Pci Function Configuration Register
    630
    
    Pci Arbiter Control Register (Pciacr)
    631
    
    Hot Swap Register Block
    632
    
    Pci Power Management Register 0 (Pcipmr)
    633
    
    Pci Power Management Register 1 (Pcipmr)
    634
  - Pci Bus Arbitration
    635
    
    Arbitration Algorithm
    636
    
    Bus Parking
    636
    
    Broken Master Lock-Out
    637
    
    Master Latency Timer
    637
    
    Bus Commands
    638
    
    Basic Transfer Control
    639
    
    Pci Protocol Fundamentals
    639
    
    Bus Driving and Turnaround
    640
    
    Byte Enable Signals
    640
    
    Device Selection
    640
    
    Bus Transactions
    641
    
    Read and Write Transactions
    641
    
    Transaction Termination
    643
    
    Fast Back-To-Back Transactions
    645
    
    Other Bus Operations
    645
    
    Data Streaming
    646
    
    Dual Address Cycles
    646
    
    Host Mode Configuration Access
    646
    
    Agent Mode Configuration Access
    647
    
    Special Cycle Command
    647
    
    Interrupt Acknowledge
    648
    
    Error Functions
    649
    
    Error Reporting
    649
    
    Pci Inbound Address Translation
    651
    
    Compactpci Hot Swap Specification Support
    652
    
    Initialization Sequence for Agent Mode
    654
    
    Initialization Sequence for Host Mode
    654
  - Sec 2.2 Architecture Overview
    656
    
    Execution Units (Eus)
    659
    
    Channel-Controlled Access
    661
    
    Sec Controller
    661
    
    Host-Controlled Access
    662
  - Configuration of Internal Memory Space
    662
  - Descriptor Overview
    664
    
    Descriptor Format: Header Dword
    665
    
    Descriptor Structure
    665
    
    Selecting Execution Units—Eu_Sel0 and Eu_Sel
    667
    
    Selecting Descriptor Type—Desc_Type
    668
    
    Descriptor Format: Pointer Dwords
    669
    
    Link Table Format
    670
    
    Descriptor Types
    672
  - Execution Units
    673
    
    Deu Mode Register (Deumr)
    673
    
    Deu Key Size Register (Deuksr)
    674
    
    Deu Data Size Register (Deudsr)
    675
    
    Deu Reset Control Register (Deurcr)
    676
    
    Deu Status Register (Deusr)
    677
    
    Deu Interrupt Status Register (Deuisr)
    678
    
    Deu Interrupt Control Register (Deuicr)
    679
    
    Deu End-Of-Message Register (Deuemr)
    681
    
    Deu IV Register (Deuiv)
    681
    
    Deu Fifos
    682
    
    Mdeu Mode Register (Mdeumr)
    682
    
    Recommended Settings for Mdeumr
    685
    
    Mdeu Data Size Register (Mdeudsr)
    686
    
    Mdeu Key Size Register (Mdeuksr)
    686
    
    Mdeu Reset Control Register (Mdeurcr)
    687
    
    Mdeu Status Register (Mdeusr)
    688
    
    Mdeu Interrupt Status Register (Mdeuisr)
    689
    
    Mdeu Interrupt Control Register (Mdeuicr)
    690
    
    Mdeu ICV Size Register
    691
    
    Mdeu Context Registers
    692
    
    Mdeu End-Of-Message Register (Mdeuemr)
    692
    
    Mdeu Key Registers
    693
    
    Aesu Mode Register (Aesumr)
    694
    
    Mdeu Fifos
    694
    
    Aesu Key Size Register (Aesuksr)
    696
    
    Aesu Data Size Register (Aesudsr)
    697
    
    Aesu Reset Control Register (Aesurcr)
    697
    
    Aesu Status Register (Aesusr)
    698
    
    Aesu Interrupt Status Register (Aesuisr)
    699
    
    Aesu Interrupt Control Register (Aesuicr)
    701
    
    Aesu End-Of-Message Register (Aesuemr)
    702
    
    Aesu Context Registers
    703
    
    Context for Cbc Mode
    704
    
    Context for CCM Mode
    704
    
    Context for Counter Mode
    704
    
    Context for Srt Mode
    704
    
    Aesu Fifos
    707
    
    Aesu Key Registers
    707
  - Channel Registers
    709
    
    Crypto-Channel Configuration Register (Cccr)
    709
    
    Crypto-Channel Pointer Status Register (Ccpsr)
    711
    
    Crypto-Channel Current Descriptor Pointer Register (Cdpr)
    716
    
    Fetch Fifo (Ff)
    716
    
    Descriptor Buffer (Db)
    717
  - Channel Interrupts
    718
    
    Channel Done Interrupt
    718
    
    Channel Error Interrupt
    718
    
    Channel Reset
    718
  - Assignment of Eus to Channel
    719
  - Bus Interface
    719
    
    Arbitration for Use of the Controller and Buses
    719
    
    Master Read
    720
    
    Master Write
    720
  - Controller Interrupts
    720
  - Controller Registers
    721
    
    Eu Assignment Status Register (Euasr)
    721
    
    Interrupt Mask Register (Imr)
    722
    
    Interrupt Status Register (Isr)
    724
    
    Interrupt Clear Register (Icr)
    725
    
    Identification Register (ID)
    727
    
    Ip Block Revision Register
    727
    
    Master Control Register (Mcr)
    728
  - Snooping by Caches
    728
  - Power Saving Mode
    729
- Chapter 15 External Signals Description
  
  736
- Chapter 16
  
  945
  - Utmi Interface
    945
  - Ulpi Interface
    946
  - Phy Clocks
    947
    
    Capability Registers Length (Caplength)
    950
    
    Host Controller Interface Version (Hciversion)
    950
    
    Host Controller Structural Parameters (Hcsparams)
    951
    
    Device Controller Interface Version (Dciversion)—Non-Ehci
    952
    
    Host Controller Capability Parameters (Hccparams)
    952
    
    Device Controller Capability Parameters (Dccparams)—Non-Ehci
    953
    
    Usb Command Register (Usbcmd)
    954
    
    Usb Interrupt Enable Register (Usbintr)
    958
    
    Frame Index Register (Frindex)
    960
    
    Control Data Structure Segment Register (Ctrldssegment)
    961
    
    Periodic Frame List Base Address Register (Periodiclistbase)
    961
    
    Current Asynchronous List Address Register (Asynclistaddr)
    963
    
    Endpoint List Address Register (Endpointlistaddr)—Non-Ehci
    963
    
    Master Interface Data Burst Size Register (Burstsize)—Non-Ehci
    964
    
    Transmit Fifo Tuning Controls Register (Txfilltuning)—Non-Ehci
    965
    
    Configure Flag Register (Configflag)
    968
    
    Port Status and Control Register (Portsc)
    968
    
    On-The-Go Status and Control (Otgsc)—Non-Ehci
    973
    
    Endpoint Setup Status Register (Endptsetupstat)—Non-Ehci
    977
    
    Endpoint Flush Register (Endptflush)—Non-Ehci
    978
    
    Endpoint Status Register (Endptstatus)—Non-Ehci
    979
    
    Endpoint Complete Register (Endptcomplete)—Non-Ehci
    980
    
    Endpoint Control Register 0 (Endptctrl0)—Non-Ehci
    981
    
    Snoop1 and Snoop2—Non-Ehci
    983
    
    Age Count Threshold Register (Age_Cnt_Thresh)—Non-Ehci
    984
    
    Priority Control Register (Pri_Ctrl)—Non-Ehci
    985
    
    System Interface Control Register (Si_Ctrl)—Non-Ehci
    986
    
    Usb General Purpose Register (Control)—Non-Ehci
    987
    
    Dma Engine
    989
    
    Fifo Ram Controller
    989
    
    System Interface
    989
    
    Phy Interface
    990
  - Host Data Structures
    990
    
    Periodic Frame List
    991
    
    Asynchronous List Queue Head Pointer
    992
    
    Isochronous (High-Speed) Transfer Descriptor (Itd)
    992
    
    Next Link Pointer
    993
    
    Itd Buffer Page Pointer List (Plus)
    994
    
    Itd Transaction Status and Control List
    994
    
    Split Transaction Isochronous Transfer Descriptor (Sitd)
    996
    
    Sitd Endpoint Capabilities/Characteristics
    997
    
    Sitd Transfer State
    998
    
    Sitd Back Link Pointer
    999
    
    Sitd Buffer Pointer List (Plus)
    999
    
    Queue Element Transfer Descriptor (Qtd)
    1000
    
    Alternate Next Qtd Pointer
    1001
    
    Next Qtd Pointer
    1001
    
    Qtd Token
    1001
    
    Qtd Buffer Page Pointer List
    1004
    
    Queue Head
    1005
    
    Queue Head Horizontal Link Pointer
    1005
    
    Transfer Overlay
    1008
    
    Periodic Frame Span Traversal Node (Fstn)
    1009
    
    Fstn Back Path Link Pointer
    1010
    
    Ftsn Normal Path Pointer
    1010
  - Host Operations
    1010
    
    Host Controller Initialization
    1011
    
    Power Port
    1012
    
    Reporting Over-Current
    1012
    
    Port Suspend/Resume
    1013
  - Schedule Traversal Rules
    1015
  - Periodic Schedule Frame Boundaries Vs. Bus Frame Boundaries
    1016
  - Periodic Schedule
    1019
  - Managing Isochronous Transfers Using Itds
    1020
    
    Host Controller Operational Model for Itds
    1021
    
    Software Operational Model for Itds
    1022
    
    Periodic Scheduling Threshold
    1024
  - Asynchronous Schedule
    1025
    
    Adding Queue Heads to Asynchronous Schedule
    1026
    
    Removing Queue Heads from Asynchronous Schedule
    1026
    
    Empty Asynchronous Schedule Detection
    1028
    
    Asynchronous Schedule Traversal: Start Event
    1029
    
    Reclamation Status Bit (Usbsts Register)
    1029
  - Managing Control/Bulk/Interrupt Transfers Via Queue Heads
    1029
    
    Buffer Pointer List Use for Data Streaming with Qtds
    1030
    
    Adding Interrupt Queue Heads to the Periodic Schedule
    1032
    
    Managing Transfer Complete Interrupts from Queue Heads
    1032
  - Ping Control
    1033
  - Split Transactions
    1034
    
    Split Transactions for Asynchronous Transfers
    1034
    
    Split Transaction Interrupt
    1036
    
    Split Transaction Scheduling Mechanisms for Interrupt
    1036
    
    Host Controller Operational Model for Fstns
    1039
    
    Software Operational Model for Fstns
    1041
    
    Split Transaction Execution State Machine for Interrupt
    1042
    
    Tracking Split Transaction Progress for Interrupt Transfers
    1042
    
    Periodic Interrupt—Do-Start-Split
    1043
    
    Periodic Interrupt—Do-Complete-Split
    1044
    
    Managing the Qh[Frametag] Field
    1047
    
    Rebalancing the Periodic Schedule
    1048
    
    Split Transaction Isochronous
    1048
    
    Split Transaction Scheduling Mechanisms for Isochronous
    1049
    
    Tracking Split Transaction Progress for Isochronous Transfers
    1053
    
    Split Transaction Execution State Machine for Isochronous
    1054
    
    Periodic Isochronous—Do-Start-Split
    1055
    
    Periodic Isochronous—Do Complete Split
    1057
    
    Complete-Split for Scheduling Boundary Cases 2A, 2B
    1060
    
    Split Transaction for Isochronous—Processing Example
    1061
    
    Port Test Modes
    1062
    
    Serial Bus Babble
    1064
    
    Transaction Error
    1064
    
    Transfer/Transaction Based Interrupts
    1064
    
    Data Buffer Error
    1065
    
    Frame List Rollover
    1066
    
    Host Controller Event Interrupts
    1066
    
    Interrupt on Async Advance
    1066
    
    Port Change Events
    1066
    
    Short Packet
    1066
    
    Usb Interrupt (Interrupt on Completion (Ioc)
    1066
    
    Host System Error
    1067
  - Device Data Structures
    1067
    
    Endpoint Queue Head
    1068
    
    Current Dtd Pointer
    1070
    
    Setup Buffer
    1070
    
    Endpoint Transfer Descriptor (Dtd)
    1071
    
    Device Controller Initialization
    1073
    
    Device Operational Model
    1073
    
    Port State and Control
    1075
    
    Bus Reset
    1077
    
    Managing Endpoints
    1078
    
    Suspend Description
    1078
    
    Suspend Operational Model
    1078
    
    Endpoint Initialization
    1079
    
    Data Toggle
    1080
    
    Data Toggle Inhibit
    1080
    
    Data Toggle Reset
    1080
    
    Device for Packet Transfers
    1081
    
    Priming Receive Endpoints
    1081
    
    Priming Transmit Endpoints
    1081
    
    Interrupt/Bulk Endpoint Operational Model
    1082
    
    Interrupt/Bulk Endpoint Bus Response Matrix
    1083
    
    Control Endpoint Operation Model
    1084
    
    Data Phase
    1084
    
    Setup Phase
    1084
    
    Control Endpoint Bus Response Matrix
    1085
    
    Status Phase
    1085
    
    Isochronous Endpoint Operational Model
    1086
    
    Isochronous Pipe Synchronization
    1087
    
    Isochronous Endpoint Bus Response Matrix
    1088
    
    Managing Queue Heads
    1088
    
    Operational Model for Setup Transfers
    1089
    
    Queue Head Initialization
    1089
    
    Building a Transfer Descriptor
    1090
    
    Managing Transfers with Transfer Descriptors
    1090
    
    Software Link Pointers
    1090
    
    Executing a Transfer Descriptor
    1091
    
    Flushing/Depriming an Endpoint
    1092
    
    Transfer Completion
    1092
    
    Device Error Matrix
    1093
    
    High-Frequency Interrupts
    1093
    
    Servicing Interrupts
    1093
    
    Error Interrupts
    1094
    
    Low-Frequency Interrupts
    1094
  - Deviations from the Ehci Specifications
    1094
    
    Embedded Transaction Translator Function
    1095
    
    Data Structures
    1096
    
    Operational Model
    1096
    
    Microframe Pipeline
    1097
    
    Split State Machines
    1097
    
    Asynchronous Transaction Scheduling and Buffer Management
    1098
    
    Device Operation
    1098
    
    Multiple Transaction Translators
    1098
    
    Periodic Transaction Scheduling and Buffer Management
    1098
    
    Embedded Design
    1099
    
    Frame Adjust Register
    1099
    
    Miscellaneous Variations from Ehci
    1099
    
    Non-Zero Fields the Register File
    1099
    
    Port Reset
    1099
    
    Sof Interrupt
    1099
    
    Port Speed Detection
    1100
  - Timing Diagrams
    1101
- Chapter 17 C Interfaces
  
  1105
  - Transaction Protocol
    1114
    
    Start Condition
    1114
    
    Slave Address Transmission
    1115
    
    Control Transfer—Implementation Details
    1116
    
    Protocol Implementation Details
    1116
    
    Repeated Start Condition
    1116
    
    Stop Condition
    1116
    
    Transaction Monitoring—Implementation Details
    1116
    
    Address Compare—Implementation Details
    1117
  - Arbitration Procedure
    1117
    
    Arbitration Control
    1118
  - Clock Control
    1118
    
    Clock Stretching
    1119
    
    Clock Synchronization
    1119
    
    Input Signal Synchronization
    1119
    
    Input Synchronization and Digital Filter
    1119
  - Boot Sequencer Mode
    1119
    
    Eeprom Data Format
    1120
    
    Using the Boot Sequencer for Reset Configuration
    1120
    
    Boot Sequencer Done Indication
    1123
  - Interrupt Service Routine Flowchart
    1123
  - Initialization Sequence
    1124
  - Generation of Start
    1125
  - Post-Transfer Software Response
    1125
  - Generation of Repeated Start
    1126
  - Generation of Stop
    1126
  - Slave Mode Interrupt Service Routine
    1126
    
    Slave Transmitter and Received Acknowledge
    1126
    
    Loss of Arbitration and Forcing of Slave Mode
    1127
  - Duart Overview
    1129
- Chapter 18
  
  1130
  - Duart Features
    1130
  - Duart External Signal Descriptions
    1131
    
    Duart Detailed Signal Descriptions
    1131
    
    Duart Signal Overview
    1131
  - Duart Modes of Operation
    1131
  - Duart Memory Map/Register Definition
    1132
    
    Duart Register Descriptions
    1133
    
    Receiver Buffer Registers (Urbr1 and Urbr)
    1133
    
    Divisor most and Least Significant Byte Registers (Udmb and Udlb)
    1134
    
    Transmitter Holding Registers (Uthr1 and Uthr)
    1134
    
    Interrupt Enable Registers (Uier1 and Uier)
    1136
    
    Interrupt ID Registers (Uiir1 and Uiir)
    1137
    
    Fifo Control Registers (Ufcr1 and Ufcr)
    1138
    
    Alternate Function Registers (Uafr1 and Uafr)
    1139
    
    Line Control Registers (Ulcr1 and Ulcr)
    1140
    
    Line Status Registers (Ulsr1 and Ulsr)
    1142
    
    Modem Control Registers (Umcr1 and Umcr)
    1142
    
    Modem Status Registers (Umsr1 and Umsr)
    1144
    
    Scratch Registers (Uscr1 and Uscr)
    1144
    
    Dma Status Registers (Udsr1 and Udsr)
    1145
    
    Data Transfer
    1147
    
    Parity Bit
    1147
    
    Serial Interface
    1147
    
    Start Bit
    1147
    
    Baud-Rate Generator Logic
    1148
    
    Local Loopback Mode
    1148
    
    Stop Bit
    1148
    
    Fifo Interrupts
    1149
    
    Fifo Mode
    1149
    
    Framing Error
    1149
    
    Overrun Error
    1149
    
    Parity Error
    1149
    
    Dma Mode Select
    1150
    
    Interrupt Control Logic
    1150
  - Duart Initialization/Application Information
    1150
- Chapter 19
  
  1155
  - Spi Transmission and Reception Process
    1155
    
    Spi as a Master Device
    1155
    
    Spi as a Slave Device
    1156
    
    Spi in Multiple-Master Operation
    1157
    
    Spi Mode Register (Spmode)
    1161
    
    Spi Event Register (Spie)
    1163
    
    Spi Mask Register (Spim)
    1164
    
    Spi Command Register (Spcom)
    1166
    
    Spi Transmit Data Hold Register (Spitd)
    1166
    
    Reverse Mode Spmode[Rev] Examples
    1167
    
    Spi Receive Data Hold Register (Spird)
    1167
  - Spi Master Programming Example
    1168
  - Spi Slave Programming Example
    1168
  - Jtag Overview
    1169
  - Jtag Signals
    1169
- Chapter 20 Jtag External Signal Descriptions
  
  1170
  - Jtag Registers and Scan Chains
    1171
- Chapter 21
  
  1175
  - Gpio Direction Register (Gpdir)
    1175
  - Gpio Open Drain Register (Gpodr)
    1175
  - Gpio Data Register (Gpdat)
    1176
  - Gpio Interrupt Event Register (Gpier)
    1176
  - Gpio Interrupt Mask Register (Gpimr)
    1176
  - Gpio Interrupt Control Register (Gpicr)
    1177
- Appendix A Revision History
  
  1179
  - Boot Memory Space
    1180
  - SYS_CLK_IN Division
    1181
    
    Byte Ordering
    1192

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Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual

Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual (1214 pages)

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