Freescale Semiconductor MPC8313 PowerQUICC II Pro Manuals

Manuals and User Guides for Freescale Semiconductor MPC8313 PowerQUICC II Pro. We have 2 Freescale Semiconductor MPC8313 PowerQUICC II Pro manuals available for free PDF download: Family Reference Manual

Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual

Freescale Semiconductor MPC8313 PowerQUICC II Pro Family Reference Manual (1250 pages)

PowerQUICC II Pro Integrated Processor  
Brand: Freescale Semiconductor | Category: Processor | Size: 9.81 MB
Table of contents
Table Of Contents3................................................................................................................................................................
About This Book75................................................................................................................................................................
General Information77................................................................................................................................................................
Related Documentation78................................................................................................................................................................
Mpc8313e Powerquicc Ii Pro Processor Overview83................................................................................................................................................................
Mpc8313e Architecture Overview89................................................................................................................................................................
Power Architecture Core89................................................................................................................................................................
Security Engine92................................................................................................................................................................
Ddr Memory Controller92................................................................................................................................................................
Dual Enhanced Three-speed Ethernet Controllers93................................................................................................................................................................
Pci Controller94................................................................................................................................................................
Pci Bus Arbitration Unit95................................................................................................................................................................
Usb Dual-role Controller96................................................................................................................................................................
Enhanced Local Bus Controller (elbc)96................................................................................................................................................................
Integrated Programmable Interrupt Controller (ipic)98................................................................................................................................................................
Dma Controller99................................................................................................................................................................
Serial Peripheral Interface (spi)100................................................................................................................................................................
System Timers100................................................................................................................................................................
Application Examples100................................................................................................................................................................
Low-end Printer Cpu And Interface Asic101................................................................................................................................................................
High-end Printer I/o Processor102................................................................................................................................................................
Ieee Std. 1588 In Test And Measurement And Industrial Automation103................................................................................................................................................................
Ieee Std. 802.11n Wlan Access Point105................................................................................................................................................................
Media Server106................................................................................................................................................................
Internal Memory Mapped Registers107................................................................................................................................................................
Accessing Immr Memory From The Local Processor107................................................................................................................................................................
Complete Immr Map107................................................................................................................................................................
Signal Descriptions141................................................................................................................................................................
Mpc8313e Powerquicc Ii Pro Integrated Processor Family Reference Manual, Rev141................................................................................................................................................................
Freescale Semiconductor141................................................................................................................................................................
Configuration Signals Sampled At Reset167................................................................................................................................................................
Output Signal States During Reset168................................................................................................................................................................
External Signals171................................................................................................................................................................
Clock Signals173................................................................................................................................................................
Functional Description174................................................................................................................................................................
Reset Causes175................................................................................................................................................................
Reset Actions175................................................................................................................................................................
Power-on Reset Flow176................................................................................................................................................................
Hard Reset Flow178................................................................................................................................................................
Soft Reset Flow179................................................................................................................................................................
Reset Configuration179................................................................................................................................................................
Reset Configuration Signals179................................................................................................................................................................
Reset Configuration Word Source180................................................................................................................................................................
Sys_clk_in Division181................................................................................................................................................................
Selecting Reset Configuration Input Signals181................................................................................................................................................................
Reset Configuration Words182................................................................................................................................................................
System Pll Configuration184................................................................................................................................................................
Pci Host/agent Configuration186................................................................................................................................................................
Boot Memory Space (bms)187................................................................................................................................................................
Boot Sequencer Configuration187................................................................................................................................................................
Boot Rom Location188................................................................................................................................................................
Etsec1 Mode189................................................................................................................................................................
Etsec2 Mode190................................................................................................................................................................
E300 Core True Little-endian191................................................................................................................................................................
Lale Configuration191................................................................................................................................................................
Loading The Reset Configuration Words191................................................................................................................................................................
Loading From Local Bus191................................................................................................................................................................
Local Bus Controller Setting192................................................................................................................................................................
Using The Boot Sequencer Reset Configuration193................................................................................................................................................................
Eeprom Data Format In Reset Configuration Mode194................................................................................................................................................................
Reset Configuration Load Fail196................................................................................................................................................................
Default Reset Configuration Words196................................................................................................................................................................
Examples For Hard-coded Reset Configuration Words Usage197................................................................................................................................................................
Clocking In Pci Host Mode200................................................................................................................................................................
Clocking In Pci Agent Mode200................................................................................................................................................................
System Clock Domains200................................................................................................................................................................
Usb Clocking201................................................................................................................................................................
Ethernet Clocking202................................................................................................................................................................
Real-time Clock (rtc)202................................................................................................................................................................
Reset Configuration Register Descriptions202................................................................................................................................................................
Reset Status Register (rsr)203................................................................................................................................................................
Reset Mode Register (rmr)204................................................................................................................................................................
Reset Protection Register (rpr)205................................................................................................................................................................
Reset Control Register (rcr)205................................................................................................................................................................
Reset Control Enable Register (rcer)206................................................................................................................................................................
Clock Configuration Registers206................................................................................................................................................................
System Pll Mode Register (spmr)207................................................................................................................................................................
Output Clock Control Register (occr)208................................................................................................................................................................
System Clock Control Register (sccr)209................................................................................................................................................................
Local Memory Map Overview And Example211................................................................................................................................................................
Address Translation And Mapping213................................................................................................................................................................
Window Into Configuration Space214................................................................................................................................................................
Local Access Windows214................................................................................................................................................................
Local Access Register Memory Map214................................................................................................................................................................
Local Access Register Descriptions216................................................................................................................................................................
Internal Memory Map Registers Base Address Register (immrbar)216................................................................................................................................................................
Updating Immrbar216................................................................................................................................................................
Alternate Configuration Base Address Register (altcbar)217................................................................................................................................................................
Lbc Local Access Window N Base Address Registers218................................................................................................................................................................
Lblawbar0[base_addr] Reset Value218................................................................................................................................................................
Pci Local Access Window N Base Address Register220................................................................................................................................................................
Pcilawbar0[base_addr] Reset Value220................................................................................................................................................................
Pci Local Access Window N Attributes Registers221................................................................................................................................................................
Pcilawar0[en] And Pcilawar0[size] Reset Value221................................................................................................................................................................
Ddr Local Access Window N Base Address Registers222................................................................................................................................................................
Ddrlawbar0[base_addr] Reset Value222................................................................................................................................................................
Ddr Local Access Window N Attributes Registers223................................................................................................................................................................
Ddrlawar0[en] And Ddrlawar0[size] Reset Value223................................................................................................................................................................
Precedence Of Local Access Windows224................................................................................................................................................................
Configuring Local Access Windows224................................................................................................................................................................
Outbound Address Translation And Mapping Windows225................................................................................................................................................................
Inbound Address Translation And Mapping Windows225................................................................................................................................................................
Pci Inbound Windows225................................................................................................................................................................
Internal Memory Map225................................................................................................................................................................
Accessing Internal Memory From External Masters226................................................................................................................................................................
System Configuration226................................................................................................................................................................
System Configuration Register Memory Map226................................................................................................................................................................
System Configuration Registers227................................................................................................................................................................
System General Purpose Register Low (sgprl)227................................................................................................................................................................
System General Purpose Register High (sgprh)227................................................................................................................................................................
System Part And Revision Id Register (spridr)228................................................................................................................................................................
Spridr[partid] Coding228................................................................................................................................................................
System Priority And Configuration Register (spcr)228................................................................................................................................................................
System I/o Configuration Register Low (sicrl)231................................................................................................................................................................
System I/o Configuration Register High (sicrh)233................................................................................................................................................................
Debug Configuration236................................................................................................................................................................
Ddr Debug Configuration237................................................................................................................................................................
Local Bus Debug Configuration237................................................................................................................................................................
Ddr Control Driver Register (ddrcdr)237................................................................................................................................................................
Ddr Debug Status Register (ddrdsr)238................................................................................................................................................................
Software Watchdog Timer (wdt)239................................................................................................................................................................
Wdt Overview239................................................................................................................................................................
Wdt Features240................................................................................................................................................................
Wdt Modes Of Operation240................................................................................................................................................................
Wdt Memory Map/register Definition241................................................................................................................................................................
System Watchdog Control Register (swcrr)241................................................................................................................................................................
System Watchdog Count Register (swcnr)242................................................................................................................................................................
System Watchdog Service Register (swsrr)243................................................................................................................................................................
Software Watchdog Timer Unit244................................................................................................................................................................
Modes Of Operation245................................................................................................................................................................
Rtc Features247................................................................................................................................................................
Rtc Modes Of Operation247................................................................................................................................................................
Rtc External Signal Description247................................................................................................................................................................
Rtc Memory Map/register Definition248................................................................................................................................................................
Real Time Counter Control Register (rtcnr)248................................................................................................................................................................
Real Time Counter Load Register (rtldr)249................................................................................................................................................................
Real Time Counter Prescale Register (rtpsr)250................................................................................................................................................................
Real Time Counter Register (rtctr)250................................................................................................................................................................
Real Time Counter Event Register (rtevr)251................................................................................................................................................................
Real Time Counter Alarm Register (rtalr)251................................................................................................................................................................
Real Time Counter Unit252................................................................................................................................................................
Rtc Operational Modes252................................................................................................................................................................
Rtc Programming Guidelines253................................................................................................................................................................
Periodic Interval Timer (pit)253................................................................................................................................................................
Pit Overview254................................................................................................................................................................
Pit Features254................................................................................................................................................................
Pit Modes Of Operation254................................................................................................................................................................
Pit External Signal Description255................................................................................................................................................................
Pit Memory Map/register Definition255................................................................................................................................................................
Periodic Interval Timer Control Register (ptcnr)256................................................................................................................................................................
Periodic Interval Timer Load Register (ptldr)256................................................................................................................................................................
Periodic Interval Timer Prescale Register (ptpsr)257................................................................................................................................................................
Periodic Interval Timer Counter Register (ptctr)257................................................................................................................................................................
Periodic Interval Timer Event Register (ptevr)258................................................................................................................................................................
Periodic Interval Timer Unit258................................................................................................................................................................
Pit Operational Modes259................................................................................................................................................................
Pit Programming Guidelines259................................................................................................................................................................
General-purpose Timers (gtms)260................................................................................................................................................................
Gtm Overview260................................................................................................................................................................
Gtm Features261................................................................................................................................................................
Gtm Modes Of Operation261................................................................................................................................................................
Clock Source Modes262................................................................................................................................................................
Gtm External Signal Description262................................................................................................................................................................
Gtm Memory Map/register Definition264................................................................................................................................................................
Global Timers Mode Registers (gtmdr1–gtmdr)268................................................................................................................................................................
Global Timers Reference Registers (gtrfr1–gtrfr)270................................................................................................................................................................
Global Timers Capture Registers (gtcpr1–gtcpr)270................................................................................................................................................................
Global Timers Counter Registers (gtcnr1–gtcnr)270................................................................................................................................................................
Global Timers Event Registers (gtevr1–gtevr)271................................................................................................................................................................
Global Timers Prescale Registers (gtpsr1–gtpsr)272................................................................................................................................................................
General-purpose Timer Units273................................................................................................................................................................
Programming Guidelines276................................................................................................................................................................
Gtm Registers276................................................................................................................................................................
Power Management Control (pmc)276................................................................................................................................................................
Pmc Memory Map/register Definition277................................................................................................................................................................
Power Management Controller Configuration Register (pmccr)278................................................................................................................................................................
Power Management Controller Event Register (pmcer)278................................................................................................................................................................
Power Management Controller Mask Register (pmcmr)280................................................................................................................................................................
Power Management Controller Configuration Register 1 (pmccr)281................................................................................................................................................................
Power Management Controller Configuration Register 2 (pmccr)283................................................................................................................................................................
Dynamic Power Management284................................................................................................................................................................
Shutting Down Unused Blocks285................................................................................................................................................................
Software-controlled Power-down States285................................................................................................................................................................
Software-controlled Power Supply Switching285................................................................................................................................................................
Support Of Pci Power Management Interface Specification286................................................................................................................................................................
Entering Low Power States—core-only Mode289................................................................................................................................................................
Entering Low Power States—core And System Mode289................................................................................................................................................................
Exiting Core And System Low Power States290................................................................................................................................................................
Exiting Low Power States—core-only Mode290................................................................................................................................................................
Exiting Low Power States—core And System Mode290................................................................................................................................................................
Mpc8313e-specific Pmc Low Power States291................................................................................................................................................................
Power State Transitions From An Acpi Perspective291................................................................................................................................................................
Mpc8313e Low Power Sequencing295................................................................................................................................................................
Pmc External Power Supply Control300................................................................................................................................................................
Low-power Considerations302................................................................................................................................................................
Core Disable In Low Power Mode303................................................................................................................................................................
Arbiter Overview305................................................................................................................................................................
Coherent System Bus Overview305................................................................................................................................................................
Arbiter Memory Map/register Definition306................................................................................................................................................................
Arbiter Configuration Register (acr)306................................................................................................................................................................
Arbiter Timers Register (atr)308................................................................................................................................................................
Arbiter Event Register (aer)310................................................................................................................................................................
Arbiter Interrupt Definition Register (aidr)311................................................................................................................................................................
Arbiter Mask Register (amr)312................................................................................................................................................................
Arbiter Event Attributes Register (aeatr)313................................................................................................................................................................
Arbiter Event Address Register (aeadr)314................................................................................................................................................................
Arbiter Event Response Register (aerr)315................................................................................................................................................................
Arbitration Policy316................................................................................................................................................................
Address Bus Arbitration With Repeat317................................................................................................................................................................
Address Bus Arbitration After Artry318................................................................................................................................................................
Address Bus Parking318................................................................................................................................................................
Data Bus Arbitration318................................................................................................................................................................
Bus Error Detection318................................................................................................................................................................
Address Time Out319................................................................................................................................................................
Data Time Out319................................................................................................................................................................
Transfer Error319................................................................................................................................................................
Address Only Transaction Type319................................................................................................................................................................
Reserved Transaction Type320................................................................................................................................................................
Illegal (eciwx/ecowx) Transaction Type320................................................................................................................................................................
Initialization/applications Information321................................................................................................................................................................
Error Handling Sequence321................................................................................................................................................................
E300c3 Overview323................................................................................................................................................................
E300c3 Features325................................................................................................................................................................
Instruction Unit328................................................................................................................................................................
Instruction Queue And Dispatch Unit328................................................................................................................................................................
Branch Processing Unit (bpu)329................................................................................................................................................................
Independent Execution Units329................................................................................................................................................................
Integer Unit (iu)329................................................................................................................................................................
Floating-point Unit (fpu)329................................................................................................................................................................
Load/store Unit (lsu)330................................................................................................................................................................
System Register Unit (sru)330................................................................................................................................................................
Completion Unit330................................................................................................................................................................
Memory Subsystem Support330................................................................................................................................................................
Memory Management Units (mmus)331................................................................................................................................................................
Cache Units332................................................................................................................................................................
Bus Interface Unit (biu)332................................................................................................................................................................
System Support Functions333................................................................................................................................................................
Power Management333................................................................................................................................................................
Time Base/decrementer333................................................................................................................................................................
Jtag Test And Debug Interface334................................................................................................................................................................
Clock Multiplier334................................................................................................................................................................
Core Performance Monitor334................................................................................................................................................................
Powerpc Architecture Implementation335................................................................................................................................................................
Implementation-specific Information335................................................................................................................................................................
Register Model336................................................................................................................................................................
Uisa Registers338................................................................................................................................................................
General-purpose Registers (gprs)338................................................................................................................................................................
Floating-point Registers (fprs)338................................................................................................................................................................
Condition Register (cr)338................................................................................................................................................................
Floating-point Status And Control Register (fpscr)338................................................................................................................................................................
User-level Sprs338................................................................................................................................................................
Vea Registers339................................................................................................................................................................
Oea Registers339................................................................................................................................................................
Machine State Register (msr)339................................................................................................................................................................
Segment Registers (srs)341................................................................................................................................................................
Supervisor-level Sprs341................................................................................................................................................................
Instruction Set And Addressing Modes348................................................................................................................................................................
Powerpc Instruction Set And Addressing Modes348................................................................................................................................................................
Implementation-specific Instruction Set349................................................................................................................................................................
Cache Implementation350................................................................................................................................................................
Powerpc Cache Characteristics350................................................................................................................................................................
Implementation-specific Cache Organization350................................................................................................................................................................
Instruction And Data Cache Way-locking352................................................................................................................................................................
Interrupt Model352................................................................................................................................................................
Powerpc Interrupt Model352................................................................................................................................................................
Implementation-specific Interrupt Model353................................................................................................................................................................
Memory Management356................................................................................................................................................................
Powerpc Memory Management356................................................................................................................................................................
Implementation-specific Memory Management356................................................................................................................................................................
Instruction Timing357................................................................................................................................................................
Core Interface358................................................................................................................................................................
Memory Accesses359................................................................................................................................................................
Debug Features360................................................................................................................................................................
Breakpoint Signaling360................................................................................................................................................................
Differences Between Cores361................................................................................................................................................................
Ipic Introduction363................................................................................................................................................................
Ipic Features366................................................................................................................................................................
Ipipc Modes Of Operation366................................................................................................................................................................
Core Enable Mode366................................................................................................................................................................
Core Disable Mode367................................................................................................................................................................
Ipic External Signal Description367................................................................................................................................................................
Ipic External Signals Overview367................................................................................................................................................................
Ipic Detailed Signal Descriptions367................................................................................................................................................................
Ipic Memory Map/register Definition368................................................................................................................................................................
System Global Interrupt Configuration Register (sicfr)369................................................................................................................................................................
System Global Interrupt Vector Register (sivcr)371................................................................................................................................................................
System Internal Interrupt Group A Priority Register (siprr_a)375................................................................................................................................................................
System Internal Interrupt Group D Priority Register (siprr_d)376................................................................................................................................................................
System Internal Interrupt Mask Register (simsr_h And Simsr_l)377................................................................................................................................................................
System Internal Interrupt Control Register (sicnr)378................................................................................................................................................................
System External Interrupt Pending Register (sepnr)380................................................................................................................................................................
System Mixed Interrupt Group A Priority Register (smprr_a)380................................................................................................................................................................
System Mixed Interrupt Group B Priority Register (smprr_b)381................................................................................................................................................................
System External Interrupt Mask Register (semsr)382................................................................................................................................................................
System External Interrupt Control Register (secnr)383................................................................................................................................................................
System Error Status Register (sersr)384................................................................................................................................................................
System Error Mask Register (sermr)385................................................................................................................................................................
System Error Control Register (sercr)386................................................................................................................................................................
System Internal Interrupt Force Registers (sifcr_h And Sifcr_l)387................................................................................................................................................................
System External Interrupt Force Register (sefcr)388................................................................................................................................................................
System Error Force Register (serfr)388................................................................................................................................................................
System Critical Interrupt Vector Register (scvcr)389................................................................................................................................................................
System Management Interrupt Vector Register (smvcr)389................................................................................................................................................................
Interrupt Types390................................................................................................................................................................
Interrupt Configuration391................................................................................................................................................................
Internal Interrupts Group Relative Priority392................................................................................................................................................................
Mixed Interrupts Group Relative Priority392................................................................................................................................................................
Highest Priority Interrupt393................................................................................................................................................................
Interrupt Source Priorities393................................................................................................................................................................
Masking Interrupt Sources396................................................................................................................................................................
Interrupt Vector Generation And Calculation397................................................................................................................................................................
Machine Check Interrupts397................................................................................................................................................................
Clock Interface Signals405................................................................................................................................................................
Debug Signals406................................................................................................................................................................
Register Descriptions407................................................................................................................................................................
Ddr Sdram Control Configuration (ddr_sdram_cfg)416................................................................................................................................................................
Ddr Sdram Mode Configuration (ddr_sdram_mode)420................................................................................................................................................................
Ddr Sdram Mode Control Register (ddr_sdram_md_cntl)422................................................................................................................................................................
Ddr Sdram Interval Configuration (ddr_sdram_interval)425................................................................................................................................................................
Ddr Sdram Data Initialization (ddr_data_init)425................................................................................................................................................................
Ddr Sdram Clock Control (ddr_sdram_clk_cntl)426................................................................................................................................................................
Ddr Initialization Address (ddr_init_addr)426................................................................................................................................................................
Ddr Ip Block Revision 1 (ddr_ip_rev)427................................................................................................................................................................
Ddr Ip Block Revision 2 (ddr_ip_rev)427................................................................................................................................................................
Ddr Sdram Interface Operation431................................................................................................................................................................
Supported Ddr Sdram Organizations432................................................................................................................................................................
Ddr Sdram Address Multiplexing433................................................................................................................................................................
Jedec Standard Ddr Sdram Interface Commands438................................................................................................................................................................
Ddr Sdram Interface Timing439................................................................................................................................................................
Clock Distribution443................................................................................................................................................................
Ddr Sdram Mode-set Command Timing443................................................................................................................................................................
Ddr Sdram Registered Dimm Mode444................................................................................................................................................................
Ddr Sdram Write Timing Adjustments444................................................................................................................................................................
Ddr Sdram Refresh445................................................................................................................................................................
Ddr Sdram Refresh Timing446................................................................................................................................................................
Ddr Sdram Refresh And Power-saving Modes446................................................................................................................................................................
Self-refresh In Sleep Mode448................................................................................................................................................................
Ddr Data Beat Ordering448................................................................................................................................................................
Page Mode And Logical Bank Retention449................................................................................................................................................................
Programming Differences Between Memory Types451................................................................................................................................................................
Ddr Sdram Initialization Sequence453................................................................................................................................................................
Elbc Bus Clock And Clock Ratios457................................................................................................................................................................
Source Id Debug Mode458................................................................................................................................................................
Option Registers (or0–or)465................................................................................................................................................................
Address Mask466................................................................................................................................................................
Upm Memory Address Register (mar)473................................................................................................................................................................
Memory Refresh Timer Prescaler Register (mrtpr)476................................................................................................................................................................
Upm/fcm Data Register (mdr)476................................................................................................................................................................
Special Operation Initiation Register (lsor)477................................................................................................................................................................
Upm Refresh Timer (lurt)478................................................................................................................................................................
Transfer Error Status Register (ltesr)479................................................................................................................................................................
Transfer Error Check Disable Register (ltedr)481................................................................................................................................................................
Transfer Error Interrupt Enable Register (lteir)482................................................................................................................................................................
Transfer Error Attributes Register (lteatr)483................................................................................................................................................................
Transfer Error Address Register (ltear)484................................................................................................................................................................
Transfer Error Ecc Register (lteccr)485................................................................................................................................................................
Local Bus Configuration Register (lbcr)485................................................................................................................................................................
Clock Ratio Register (lcrr)487................................................................................................................................................................
Flash Mode Register (fmr)488................................................................................................................................................................
Flash Instruction Register (fir)489................................................................................................................................................................
Flash Command Register (fcr)490................................................................................................................................................................
Flash Block Address Register (fbar)491................................................................................................................................................................
Flash Page Address Register (fpar)491................................................................................................................................................................
Flash Byte Count Register (fbcr)493................................................................................................................................................................
Basic Architecture495................................................................................................................................................................
Address And Address Space Checking495................................................................................................................................................................
External Address Latch Enable Signal (lale)496................................................................................................................................................................
Data Transfer Acknowledge (ta)497................................................................................................................................................................
Data Buffer Control (lbctl)498................................................................................................................................................................
Atomic Operation498................................................................................................................................................................
Bus Monitor499................................................................................................................................................................
General-purpose Chip-select Machine (gpcm)499................................................................................................................................................................
Gpcm Read Signal Timing500................................................................................................................................................................
Gpcm Write Signal Timing502................................................................................................................................................................
Chip-select Assertion Timing504................................................................................................................................................................
Programmable Wait State Configuration505................................................................................................................................................................
Chip-select And Write Enable Negation Timing505................................................................................................................................................................
Relaxed Timing506................................................................................................................................................................
Output Enable (loe) Timing509................................................................................................................................................................
External Access Termination (lgta)510................................................................................................................................................................
Gpcm Boot Chip-select Operation511................................................................................................................................................................
Flash Control Machine (fcm)512................................................................................................................................................................
Fcm Buffer Ram514................................................................................................................................................................
Buffer Layout And Page Mapping For Small-page Nand Flash Devices515................................................................................................................................................................
Buffer Layout And Page Mapping For Large-page Nand Flash Devices516................................................................................................................................................................
Error Correcting Codes And The Spare Region517................................................................................................................................................................
Programming Fcm518................................................................................................................................................................
Fcm Command Instructions519................................................................................................................................................................
Fcm No-operation Instruction520................................................................................................................................................................
Fcm Address Instructions520................................................................................................................................................................
Fcm Data Read Instructions520................................................................................................................................................................
Fcm Data Write Instructions521................................................................................................................................................................
Fcm Signal Timing521................................................................................................................................................................
Fcm Chip-select Timing521................................................................................................................................................................
Fcm Command, Address, And Write Data Timing522................................................................................................................................................................
Fcm Ready/busy Timing523................................................................................................................................................................
Fcm Read Data Timing524................................................................................................................................................................
Fcm Extended Read Hold Timing525................................................................................................................................................................
Fcm Boot Chip-select Operation525................................................................................................................................................................
Fcm Bank 0 Reset Initialization526................................................................................................................................................................
Boot Block Loading Into The Fcm Buffer Ram526................................................................................................................................................................
User-programmable Machines (upms)528................................................................................................................................................................
Upm Requests529................................................................................................................................................................
Memory Access Requests530................................................................................................................................................................
Upm Refresh Timer Requests530................................................................................................................................................................
Software Requests—run Command531................................................................................................................................................................
Exception Requests531................................................................................................................................................................
Programming The Upms531................................................................................................................................................................
Upm Programming Example (two Sequential Writes To The Ram Array)532................................................................................................................................................................
Upm Programming Example (two Sequential Reads From The Ram Array)533................................................................................................................................................................
Upm Signal Timing533................................................................................................................................................................
Ram Array534................................................................................................................................................................
Ram Words534................................................................................................................................................................
Loop Control (loop)540................................................................................................................................................................
Repeat Execution Of Current Ram Word (redo)541................................................................................................................................................................
Address Multiplexing (amx)541................................................................................................................................................................
Data Valid And Data Sample Control (uta)543................................................................................................................................................................
Lgpl[0:5] Signal Negation (last)543................................................................................................................................................................
Wait Mechanism (waen)543................................................................................................................................................................
Interfacing To Peripherals In Different Address Modes545................................................................................................................................................................
Multiplexed Address/data Bus For 26-bit Addressing545................................................................................................................................................................
Non-multiplexed Address And Data Buses545................................................................................................................................................................
Peripheral Hierarchy On The Local Bus For High Bus Speeds546................................................................................................................................................................
Gpcm Timings547................................................................................................................................................................
Bus Turnaround547................................................................................................................................................................
Address Phase After Previous Read548................................................................................................................................................................
Read Data Phase After Address Phase548................................................................................................................................................................
Read-modify-write Cycle For Parity Protected Memory Banks548................................................................................................................................................................
Upm Cycles With Additional Address Phases548................................................................................................................................................................
Interface To Different Port-size Devices548................................................................................................................................................................
Command Sequence Examples For Nand Flash Eeprom550................................................................................................................................................................
Nand Flash Soft Reset Command Sequence Example550................................................................................................................................................................
Nand Flash Read Status Command Sequence Example551................................................................................................................................................................
Nand Flash Read Identification Command Sequence Example551................................................................................................................................................................
Nand Flash Page Read Command Sequence Example552................................................................................................................................................................
Nand Flash Block Erase Command Sequence Example552................................................................................................................................................................
Nand Flash Program Command Sequence Example553................................................................................................................................................................
Interfacing To Fast-page Mode Dram Using Upm554................................................................................................................................................................
Interfacing To Zbt Sram Using Upm559................................................................................................................................................................
Sequencer Overview563................................................................................................................................................................
Sequencer Features564................................................................................................................................................................
Sequencer External Signal Description564................................................................................................................................................................
Sequencer Memory Map/register Definition564................................................................................................................................................................
Sequencer Register Descriptions565................................................................................................................................................................
Power Management Control Register (pmcr)567................................................................................................................................................................
Discard Timer Control Register (dtcr)568................................................................................................................................................................
Transaction Forwarding568................................................................................................................................................................
Transactions From The Coherency System Bus (csb) Port569................................................................................................................................................................
Transactions From The Pci Port569................................................................................................................................................................
Transactions From The Dma Port569................................................................................................................................................................
Pci Outbound Address Translation569................................................................................................................................................................
Transaction Ordering570................................................................................................................................................................
Dma Features571................................................................................................................................................................
Dma Memory Map/register Definition572................................................................................................................................................................
Dma Register Descriptions573................................................................................................................................................................
Outbound Message Interrupt Status Register (omisr)573................................................................................................................................................................
Outbound Message Interrupt Mask Register (omimr)574................................................................................................................................................................
Inbound Message Registers (imr0–imr)575................................................................................................................................................................
Outbound Message Registers (omr0–omr)575................................................................................................................................................................
Doorbell Registers576................................................................................................................................................................
Outbound Doorbell Register (odr)576................................................................................................................................................................
Inbound Doorbell Register (idr)577................................................................................................................................................................
Inbound Message Interrupt Status Register (imisr)577................................................................................................................................................................
Inbound Message Interrupt Mask Register (imimr)578................................................................................................................................................................
Dma Registers579................................................................................................................................................................
Dma General Status Register (dmagsr)585................................................................................................................................................................
Message Unit585................................................................................................................................................................
Messaging Registers (imr0–imr1, Omr0–omr)585................................................................................................................................................................
Doorbell Registers (idr And Odr)586................................................................................................................................................................
Dma Operation586................................................................................................................................................................
Dma Coherency587................................................................................................................................................................
Halt And Error Conditions588................................................................................................................................................................
Dma Segment Descriptors588................................................................................................................................................................
Descriptor In Big-endian Mode589................................................................................................................................................................
Descriptor In Little-endian Mode590................................................................................................................................................................
Initialization Steps In Direct Mode590................................................................................................................................................................
Initialization Steps In Chaining Mode591................................................................................................................................................................
Pci Introduction593................................................................................................................................................................
Pci Features595................................................................................................................................................................
Pci Modes Of Operation595................................................................................................................................................................
Host/agent Mode Configuration595................................................................................................................................................................
Pci Arbiter Configuration596................................................................................................................................................................
Pci External Signal Description596................................................................................................................................................................
Pci Memory Map/register Definitions603................................................................................................................................................................
Pci Configuration Access Registers605................................................................................................................................................................
Pci Interrupt Acknowledge Register (pci_int_ack)607................................................................................................................................................................
Pci Memory-mapped Control And Status Registers607................................................................................................................................................................
Pci Error Status Register (pci_esr)607................................................................................................................................................................
Pci Error Capture Disable Register (pci_ecdr)608................................................................................................................................................................
Pci Error Enable Register (pci_eer)609................................................................................................................................................................
Pci Error Attributes Capture Register (pci_eatcr)610................................................................................................................................................................
Pci Error Address Capture Register (pci_eacr)611................................................................................................................................................................
Pci Error Extended Address Capture Register (pci_eeacr)612................................................................................................................................................................
Pci Error Data Low Capture Register (pci_edlcr)612................................................................................................................................................................
Pci General Control Register (pci_gcr)612................................................................................................................................................................
Pci Error Control Register (pci_ecr)613................................................................................................................................................................
Pci General Status Register (pci_gsr)614................................................................................................................................................................
Pci Configuration Space Registers617................................................................................................................................................................
Vendor Id Configuration Register619................................................................................................................................................................
Device Id Configuration Register619................................................................................................................................................................
Pci Command Configuration Register620................................................................................................................................................................
Pci Status Configuration Register621................................................................................................................................................................
Revision Id Configuration Register622................................................................................................................................................................
Standard Programming Interface Configuration Register622................................................................................................................................................................
Subclass Code Configuration Register623................................................................................................................................................................
Base Class Code Configuration Register623................................................................................................................................................................
Cache Line Size Configuration Register624................................................................................................................................................................
Latency Timer Configuration Register624................................................................................................................................................................
Header Type Configuration Register625................................................................................................................................................................
Bist Control Configuration Register625................................................................................................................................................................
Pimmr Base Address Configuration Register625................................................................................................................................................................
Gpl Base Address Register626................................................................................................................................................................
Subsystem Vendor Id Configuration Register628................................................................................................................................................................
Subsystem Device Id Configuration Register628................................................................................................................................................................
Capabilities Pointer Configuration Register628................................................................................................................................................................
Interrupt Line Configuration Register629................................................................................................................................................................
Interrupt Pin Configuration Register629................................................................................................................................................................
Minimum Grant Configuration Register629................................................................................................................................................................
Maximum Latency Configuration Register630................................................................................................................................................................
Pci Function Configuration Register630................................................................................................................................................................
Pci Arbiter Control Register (pciacr)631................................................................................................................................................................
Hot Swap Register Block632................................................................................................................................................................
Pci Power Management Register 0 (pcipmr)633................................................................................................................................................................
Pci Power Management Register 1 (pcipmr)634................................................................................................................................................................
Pci Bus Arbitration635................................................................................................................................................................
Bus Parking636................................................................................................................................................................
Arbitration Algorithm636................................................................................................................................................................
Broken Master Lock-out637................................................................................................................................................................
Master Latency Timer637................................................................................................................................................................
Bus Commands638................................................................................................................................................................
Pci Protocol Fundamentals639................................................................................................................................................................
Basic Transfer Control639................................................................................................................................................................
Device Selection640................................................................................................................................................................
Byte Enable Signals640................................................................................................................................................................
Bus Driving And Turnaround640................................................................................................................................................................
Bus Transactions641................................................................................................................................................................
Read And Write Transactions641................................................................................................................................................................
Transaction Termination643................................................................................................................................................................
Other Bus Operations645................................................................................................................................................................
Fast Back-to-back Transactions645................................................................................................................................................................
Dual Address Cycles646................................................................................................................................................................
Data Streaming646................................................................................................................................................................
Host Mode Configuration Access646................................................................................................................................................................
Agent Mode Configuration Access647................................................................................................................................................................
Special Cycle Command647................................................................................................................................................................
Interrupt Acknowledge648................................................................................................................................................................
Error Functions649................................................................................................................................................................
Error Reporting649................................................................................................................................................................
Pci Inbound Address Translation651................................................................................................................................................................
Compactpci Hot Swap Specification Support652................................................................................................................................................................
Initialization Sequence For Host Mode654................................................................................................................................................................
Initialization Sequence For Agent Mode654................................................................................................................................................................
Sec 2.2 Architecture Overview656................................................................................................................................................................
Execution Units (eus)659................................................................................................................................................................
Sec Controller661................................................................................................................................................................
Channel-controlled Access661................................................................................................................................................................
Host-controlled Access662................................................................................................................................................................
Configuration Of Internal Memory Space662................................................................................................................................................................
Descriptor Overview664................................................................................................................................................................
Descriptor Structure665................................................................................................................................................................
Descriptor Format: Header Dword665................................................................................................................................................................
Selecting Execution Units—eu_sel0 And Eu_sel667................................................................................................................................................................
Selecting Descriptor Type—desc_type668................................................................................................................................................................
Descriptor Format: Pointer Dwords669................................................................................................................................................................
Link Table Format670................................................................................................................................................................
Descriptor Types672................................................................................................................................................................
Execution Units673................................................................................................................................................................
Deu Mode Register (deumr)673................................................................................................................................................................
Deu Key Size Register (deuksr)674................................................................................................................................................................
Deu Data Size Register (deudsr)675................................................................................................................................................................
Deu Reset Control Register (deurcr)676................................................................................................................................................................
Deu Status Register (deusr)677................................................................................................................................................................
Deu Interrupt Status Register (deuisr)678................................................................................................................................................................
Deu Interrupt Control Register (deuicr)679................................................................................................................................................................
Deu End-of-message Register (deuemr)681................................................................................................................................................................
Deu Iv Register (deuiv)681................................................................................................................................................................
Deu Fifos682................................................................................................................................................................
Mdeu Mode Register (mdeumr)682................................................................................................................................................................
Recommended Settings For Mdeumr685................................................................................................................................................................
Mdeu Key Size Register (mdeuksr)686................................................................................................................................................................
Mdeu Data Size Register (mdeudsr)686................................................................................................................................................................
Mdeu Reset Control Register (mdeurcr)687................................................................................................................................................................
Mdeu Status Register (mdeusr)688................................................................................................................................................................
Mdeu Interrupt Status Register (mdeuisr)689................................................................................................................................................................
Mdeu Interrupt Control Register (mdeuicr)690................................................................................................................................................................
Mdeu Icv Size Register691................................................................................................................................................................
Mdeu End-of-message Register (mdeuemr)692................................................................................................................................................................
Mdeu Context Registers692................................................................................................................................................................
Mdeu Key Registers693................................................................................................................................................................
Mdeu Fifos694................................................................................................................................................................
Aesu Mode Register (aesumr)694................................................................................................................................................................
Aesu Key Size Register (aesuksr)696................................................................................................................................................................
Aesu Data Size Register (aesudsr)697................................................................................................................................................................
Aesu Reset Control Register (aesurcr)697................................................................................................................................................................
Aesu Status Register (aesusr)698................................................................................................................................................................
Aesu Interrupt Status Register (aesuisr)699................................................................................................................................................................
Aesu Interrupt Control Register (aesuicr)701................................................................................................................................................................
Aesu End-of-message Register (aesuemr)702................................................................................................................................................................
Aesu Context Registers703................................................................................................................................................................
Context For Cbc Mode704................................................................................................................................................................
Context For Counter Mode704................................................................................................................................................................
Context For Srt Mode704................................................................................................................................................................
Context For Ccm Mode704................................................................................................................................................................
Aesu Key Registers707................................................................................................................................................................
Aesu Fifos707................................................................................................................................................................
Channel Registers709................................................................................................................................................................
Crypto-channel Configuration Register (cccr)709................................................................................................................................................................
Crypto-channel Pointer Status Register (ccpsr)711................................................................................................................................................................
Crypto-channel Current Descriptor Pointer Register (cdpr)716................................................................................................................................................................
Fetch Fifo (ff)716................................................................................................................................................................
Descriptor Buffer (db)717................................................................................................................................................................
Channel Interrupts718................................................................................................................................................................
Channel Done Interrupt718................................................................................................................................................................
Channel Error Interrupt718................................................................................................................................................................
Channel Reset718................................................................................................................................................................
Assignment Of Eus To Channel719................................................................................................................................................................
Bus Interface719................................................................................................................................................................
Arbitration For Use Of The Controller And Buses719................................................................................................................................................................
Master Read720................................................................................................................................................................
Master Write720................................................................................................................................................................
Controller Interrupts720................................................................................................................................................................
Controller Registers721................................................................................................................................................................
Eu Assignment Status Register (euasr)721................................................................................................................................................................
Interrupt Mask Register (imr)722................................................................................................................................................................
Interrupt Status Register (isr)724................................................................................................................................................................
Interrupt Clear Register (icr)725................................................................................................................................................................
Identification Register (id)727................................................................................................................................................................
Ip Block Revision Register727................................................................................................................................................................
Master Control Register (mcr)728................................................................................................................................................................
Snooping By Caches728................................................................................................................................................................
Power Saving Mode729................................................................................................................................................................
External Signals Description736................................................................................................................................................................
Top-level Module Memory Map741................................................................................................................................................................
Detailed Memory Map742................................................................................................................................................................
Memory-mapped Register Descriptions752................................................................................................................................................................
Etsec General Control And Status Registers752................................................................................................................................................................
Interrupt Event Register (ievent)754................................................................................................................................................................
Interrupt Mask Register (imask)758................................................................................................................................................................
Error Disabled Register (edis)760................................................................................................................................................................
Ethernet Control Register (ecntrl)761................................................................................................................................................................
Pause Time Value Register (ptv)763................................................................................................................................................................
Dma Control Register (dmactrl)764................................................................................................................................................................
Etsec Transmit Control And Status Registers766................................................................................................................................................................
Transmit Control Register (tctrl)766................................................................................................................................................................
Transmit Status Register (tstat)768................................................................................................................................................................
Default Vlan Control Word Register (dfvlan)772................................................................................................................................................................
Transmit Interrupt Coalescing Register (txic)773................................................................................................................................................................
Transmit Queue Control Register (tqueue)774................................................................................................................................................................
Txbd Ring 0–3 Weighting Register (tr03wt)774................................................................................................................................................................
Txbd Ring 4–7 Weighting Register (tr47wt)775................................................................................................................................................................
Transmit Data Buffer Pointer High Register (tbdbph)776................................................................................................................................................................
Transmit Buffer Descriptor Pointers 0–7 (tbptr0–tbptr)776................................................................................................................................................................
Transmit Descriptor Base Address Registers (tbase0–tbase)777................................................................................................................................................................
Transmit Time Stamp Identification Register (tmr_txts1–2_id)778................................................................................................................................................................
Transmit Time Stamp Register (tmr_txts1–2_h/l)778................................................................................................................................................................
Etsec Receive Control And Status Registers779................................................................................................................................................................
Receive Control Register (rctrl)779................................................................................................................................................................
Receive Status Register (rstat)781................................................................................................................................................................
Receive Queue Control Register (rqueue)784................................................................................................................................................................
Receive Bit Field Extract Control Register (rbifx)784................................................................................................................................................................
Receive Queue Filer Table Address Register (rqfar)786................................................................................................................................................................
Receive Queue Filer Table Control Register (rqfcr)786................................................................................................................................................................
Receive Queue Filer Table Property Register (rqfpr)788................................................................................................................................................................
Maximum Receive Buffer Length Register (mrblr)791................................................................................................................................................................
Receive Data Buffer Pointer High Register (rbdbph)792................................................................................................................................................................
Receive Buffer Descriptor Pointers 0–7 (rbptr0–rbptr)792................................................................................................................................................................
Receive Descriptor Base Address Registers (rbase0–rbase)793................................................................................................................................................................
Receive Stamp Register (tmr_rxts_h/l)793................................................................................................................................................................
Mac Functionality794................................................................................................................................................................
Configuring The Mac794................................................................................................................................................................
Controlling Csma/cd794................................................................................................................................................................
Handling Packet Collisions795................................................................................................................................................................
Controlling Packet Flow795................................................................................................................................................................
Controlling Phy Links796................................................................................................................................................................
Mac Registers797................................................................................................................................................................
Mac Configuration 1 Register (maccfg)797................................................................................................................................................................
Mac Configuration 2 Register (maccfg)798................................................................................................................................................................
Inter-packet Gap/inter-frame Gap Register (ipgifg)800................................................................................................................................................................
Half-duplex Register (hafdup)801................................................................................................................................................................
Maximum Frame Length Register (maxfrm)802................................................................................................................................................................
Mii Management Configuration Register (miimcfg)802................................................................................................................................................................
Mii Management Command Register (miimcom)803................................................................................................................................................................
Mii Management Address Register (miimadd)804................................................................................................................................................................
Mii Management Control Register (miimcon)805................................................................................................................................................................
Mii Management Status Register (miimstat)805................................................................................................................................................................
Mii Management Indicator Register (miimind)806................................................................................................................................................................
Interface Status Register (ifstat)806................................................................................................................................................................
Mac Station Address Part 1 Register (macstnaddr)807................................................................................................................................................................
Mac Station Address Part 2 Register (macstnaddr)808................................................................................................................................................................
Mac Exact Match Address 1–15 Part 1 Registers808................................................................................................................................................................
Mac Exact Match Address 1–15 Part 2 Registers809................................................................................................................................................................
Mib Registers809................................................................................................................................................................
Transmit And Receive 64-byte Frame Counter (tr)810................................................................................................................................................................
Transmit And Receive 65- To 127-byte Frame Counter (tr)811................................................................................................................................................................
Transmit And Receive 128- To 255-byte Frame Counter (tr)811................................................................................................................................................................
Transmit And Receive 256- To 511-byte Frame Counter (tr)812................................................................................................................................................................
Transmit And Receive 512- To 1023-byte Frame Counter (tr1k)812................................................................................................................................................................
Transmit And Receive 1024- To 1518-byte Frame Counter (trmax)813................................................................................................................................................................
Transmit And Receive 1519- To 1522-byte Vlan Frame Counter (trmgv)813................................................................................................................................................................
Receive Byte Counter (rbyt)814................................................................................................................................................................
Receive Packet Counter (rpkt)814................................................................................................................................................................
Receive Fcs Error Counter (rfcs)814................................................................................................................................................................
Receive Multicast Packet Counter (rmca)815................................................................................................................................................................
Receive Broadcast Packet Counter (rbca)815................................................................................................................................................................
Receive Control Frame Packet Counter (rxcf)816................................................................................................................................................................
Receive Pause Frame Packet Counter (rxpf)816................................................................................................................................................................
Receive Unknown Opcode Packet Counter (rxuo)817................................................................................................................................................................
Receive Alignment Error Counter (raln)817................................................................................................................................................................
Receive Frame Length Error Counter (rflr)818................................................................................................................................................................
Receive Code Error Counter (rcde)818................................................................................................................................................................
Receive Carrier Sense Error Counter (rcse)819................................................................................................................................................................
Receive Undersize Packet Counter (rund)819................................................................................................................................................................
Receive Oversize Packet Counter (rovr)820................................................................................................................................................................
Receive Fragments Counter (rfrg)820................................................................................................................................................................
Receive Jabber Counter (rjbr)821................................................................................................................................................................
Receive Dropped Packet Counter (rdrp)821................................................................................................................................................................
Transmit Byte Counter (tbyt)822................................................................................................................................................................
Transmit Packet Counter (tpkt)822................................................................................................................................................................
Transmit Multicast Packet Counter (tmca)823................................................................................................................................................................
Transmit Broadcast Packet Counter (tbca)823................................................................................................................................................................
Transmit Pause Control Frame Counter (txpf)824................................................................................................................................................................
Transmit Deferral Packet Counter (tdfr)824................................................................................................................................................................
Transmit Excessive Deferral Packet Counter (tedf)825................................................................................................................................................................
Transmit Single Collision Packet Counter (tscl)825................................................................................................................................................................
Transmit Multiple Collision Packet Counter (tmcl)826................................................................................................................................................................
Transmit Late Collision Packet Counter (tlcl)826................................................................................................................................................................
Transmit Excessive Collision Packet Counter (txcl)827................................................................................................................................................................
Transmit Total Collision Counter (tncl)827................................................................................................................................................................
Transmit Drop Frame Counter (tdrp)828................................................................................................................................................................
Transmit Jabber Frame Counter (tjbr)828................................................................................................................................................................
Transmit Fcs Error Counter (tfcs)829................................................................................................................................................................
Transmit Control Frame Counter (txcf)829................................................................................................................................................................
Transmit Oversize Frame Counter (tovr)830................................................................................................................................................................
Transmit Undersize Frame Counter (tund)830................................................................................................................................................................
Transmit Fragment Counter (tfrg)831................................................................................................................................................................
Carry Register 1 (car)831................................................................................................................................................................
Carry Register 2 (car)833................................................................................................................................................................
Carry Mask Register 1 (cam)834................................................................................................................................................................
Carry Mask Register 2 (cam)835................................................................................................................................................................
Receive Filer Rejected Packet Counter (rrej)836................................................................................................................................................................
Hash Function Registers837................................................................................................................................................................
Dma Attribute Registers838................................................................................................................................................................
Attribute Register (attr)838................................................................................................................................................................
Lossless Flow Control Configuration Registers839................................................................................................................................................................
Receive Queue Parameters 0–7 (rqprm0–pqprm)839................................................................................................................................................................
Ieee 1588-compatible Timestamping Registers840................................................................................................................................................................
Timer Event Register (tmr_tevent)843................................................................................................................................................................
Timer Event Mask Register (tmr_temask)844................................................................................................................................................................
Timer Ptp Packet Event Register (tmr_pevent)845................................................................................................................................................................
Timer Event Mask Register (tmr_pemask)846................................................................................................................................................................
Timer Status Register (tmr_stat)846................................................................................................................................................................
Timer Counter Register (tmr_cnt_h/l)847................................................................................................................................................................
Timer Drift Compensation Addend Register (tmr_add)848................................................................................................................................................................
Timer Accumulator Register (tmr_acc)849................................................................................................................................................................
Timer Prescale Register (tmr_prsc)849................................................................................................................................................................
Timer Offset Register (tmroff_h/l)849................................................................................................................................................................
Alarm Time Comparator Register (tmr_alarm1–2_h/l)850................................................................................................................................................................
External Trigger Stamp Register (tmr_etts1–2_h/l)852................................................................................................................................................................
Ten-bit Interface (tbi)852................................................................................................................................................................
Tbi Transmit Process852................................................................................................................................................................
Packet Encapsulation852................................................................................................................................................................
B10b Encoding853................................................................................................................................................................
Preamble Shortening853................................................................................................................................................................
Tbi Receive Process853................................................................................................................................................................
Auto-negotiation For 1000base-x853................................................................................................................................................................
Tbi Mii Set Register Descriptions854................................................................................................................................................................
Control Register (cr)855................................................................................................................................................................
Status Register (sr)856................................................................................................................................................................
An Advertisement Register (ana)857................................................................................................................................................................
An Link Partner Base Page Ability Register (anlpbpa)859................................................................................................................................................................
An Expansion Register (anex)860................................................................................................................................................................
An Next Page Transmit Register (annpt)860................................................................................................................................................................
An Link Partner Ability Next Page Register (anlpanp)861................................................................................................................................................................
Extended Status Register (exst)862................................................................................................................................................................
Jitter Diagnostics Register (jd)863................................................................................................................................................................
Tbi Control Register (tbicon)864................................................................................................................................................................
Connecting To Physical Interfaces On Ethernet865................................................................................................................................................................
Media-independent Interface (mii)866................................................................................................................................................................
Reduced Media-independent Interface (rmii)866................................................................................................................................................................
Reduced Gigabit Media-independent Interface (rgmii)867................................................................................................................................................................
Reduced Ten-bit Interface (rtbi)868................................................................................................................................................................
Ethernet Physical Interfaces Signal Summary871................................................................................................................................................................
Gigabit Ethernet Controller Channel Operation873................................................................................................................................................................
Hardware Controlled Initialization873................................................................................................................................................................
User Initialization873................................................................................................................................................................
Soft Reset And Reconfiguring Procedure874................................................................................................................................................................
Gigabit Ethernet Frame Transmission875................................................................................................................................................................
Gigabit Ethernet Frame Reception876................................................................................................................................................................
Ethernet Preamble Customization878................................................................................................................................................................
User-defined Preamble Transmission878................................................................................................................................................................
User-visible Preamble Reception879................................................................................................................................................................
Rmon Support879................................................................................................................................................................
Frame Recognition880................................................................................................................................................................
Destination Address Recognition And Frame Filtering881................................................................................................................................................................
Hash Table Algorithm882................................................................................................................................................................
Magic Packet Mode884................................................................................................................................................................
Flow Control884................................................................................................................................................................
Interrupt Handling885................................................................................................................................................................
Interrupt Coalescing886................................................................................................................................................................
Interrupt Coalescing By Frame Count Threshold886................................................................................................................................................................
Interrupt Coalescing By Timer Threshold887................................................................................................................................................................
Inter-frame Gap Time888................................................................................................................................................................
Internal And External Loop Back888................................................................................................................................................................
Error-handling Procedure888................................................................................................................................................................
Tcp/ip Off-load890................................................................................................................................................................
Frame Control Blocks891................................................................................................................................................................
Transmit Path Off-load And Tx Ptp Packet Parsing892................................................................................................................................................................
Receive Path Off-load893................................................................................................................................................................
Quality Of Service (qos) Provision895................................................................................................................................................................
Receive Parser895................................................................................................................................................................
Receive Queue Filer897................................................................................................................................................................
Filing Rules898................................................................................................................................................................
Comparing Properties With Bit Masks899................................................................................................................................................................
Special-case Rules900................................................................................................................................................................
Filer Interrupt Events900................................................................................................................................................................
Setting Up The Receive Queue Filer Table901................................................................................................................................................................
Filer Example—802.1p Priority Filing901................................................................................................................................................................
Filer Example—ip Diff-serv Code Points Filing902................................................................................................................................................................
Filer Example—tcp And Udp Port Filing902................................................................................................................................................................
Transmission Scheduling905................................................................................................................................................................
Priority-based Queuing (pbq)905................................................................................................................................................................
Modified Weighted Round-robin Queuing (mwrr)906................................................................................................................................................................
Lossless Flow Control907................................................................................................................................................................
Back Pressure Determination Through Free Buffers907................................................................................................................................................................
Software Use Of Hardware-initiated Back Pressure909................................................................................................................................................................
Hardware Assist For Ieee 1588-compatible Timestamping909................................................................................................................................................................
Timer Logic Overview911................................................................................................................................................................
Time-stamp Insertion On The Received Packets911................................................................................................................................................................
Timestamp Point911................................................................................................................................................................
Ptp Packet Parsing912................................................................................................................................................................
General Purpose Filer Rule913................................................................................................................................................................
Time-stamp Insertion On Transmit Packets913................................................................................................................................................................
Buffer Descriptors916................................................................................................................................................................
Data Buffer Descriptors916................................................................................................................................................................
Transmit Data Buffer Descriptors (txbd)918................................................................................................................................................................
Receive Buffer Descriptors (rxbd)921................................................................................................................................................................
Interface Mode Configuration923................................................................................................................................................................
Mii Interface Mode924................................................................................................................................................................
Rgmii Interface Mode927................................................................................................................................................................
Rmii Interface Mode931................................................................................................................................................................
Rtbi Interface Mode935................................................................................................................................................................
Sgmii Interface Support938................................................................................................................................................................
Utmi Interface945................................................................................................................................................................
Ulpi Interface946................................................................................................................................................................
Phy Clocks947................................................................................................................................................................
Capability Registers Length (caplength)950................................................................................................................................................................
Host Controller Interface Version (hciversion)950................................................................................................................................................................
Host Controller Structural Parameters (hcsparams)951................................................................................................................................................................
Host Controller Capability Parameters (hccparams)952................................................................................................................................................................
Device Controller Interface Version (dciversion)—non-ehci952................................................................................................................................................................
Device Controller Capability Parameters (dccparams)—non-ehci953................................................................................................................................................................
Usb Command Register (usbcmd)954................................................................................................................................................................
Usb Interrupt Enable Register (usbintr)958................................................................................................................................................................
Frame Index Register (frindex)960................................................................................................................................................................
Control Data Structure Segment Register (ctrldssegment)961................................................................................................................................................................
Periodic Frame List Base Address Register (periodiclistbase)961................................................................................................................................................................
Current Asynchronous List Address Register (asynclistaddr)963................................................................................................................................................................
Endpoint List Address Register (endpointlistaddr)—non-ehci963................................................................................................................................................................
Master Interface Data Burst Size Register (burstsize)—non-ehci964................................................................................................................................................................
Transmit Fifo Tuning Controls Register (txfilltuning)—non-ehci965................................................................................................................................................................
Configure Flag Register (configflag)968................................................................................................................................................................
Port Status And Control Register (portsc)968................................................................................................................................................................
On-the-go Status And Control (otgsc)—non-ehci973................................................................................................................................................................
Endpoint Setup Status Register (endptsetupstat)—non-ehci977................................................................................................................................................................
Endpoint Initialization Register (endptprime)—non-ehci978................................................................................................................................................................
Endpoint Flush Register (endptflush)—non-ehci978................................................................................................................................................................
Endpoint Status Register (endptstatus)—non-ehci979................................................................................................................................................................
Endpoint Complete Register (endptcomplete)—non-ehci980................................................................................................................................................................
Endpoint Control Register 0 (endptctrl0)—non-ehci981................................................................................................................................................................
Snoop1 And Snoop2—non-ehci983................................................................................................................................................................
Age Count Threshold Register (age_cnt_thresh)—non-ehci984................................................................................................................................................................
Priority Control Register (pri_ctrl)—non-ehci985................................................................................................................................................................
System Interface Control Register (si_ctrl)—non-ehci986................................................................................................................................................................
Usb General Purpose Register (control)—non-ehci987................................................................................................................................................................
System Interface989................................................................................................................................................................
Dma Engine989................................................................................................................................................................
Fifo Ram Controller989................................................................................................................................................................
Phy Interface990................................................................................................................................................................
Host Data Structures990................................................................................................................................................................
Periodic Frame List991................................................................................................................................................................
Asynchronous List Queue Head Pointer992................................................................................................................................................................
Isochronous (high-speed) Transfer Descriptor (itd)992................................................................................................................................................................
Next Link Pointer993................................................................................................................................................................
Itd Transaction Status And Control List994................................................................................................................................................................
Itd Buffer Page Pointer List (plus)994................................................................................................................................................................
Split Transaction Isochronous Transfer Descriptor (sitd)996................................................................................................................................................................
Sitd Endpoint Capabilities/characteristics997................................................................................................................................................................
Sitd Transfer State998................................................................................................................................................................
Sitd Buffer Pointer List (plus)999................................................................................................................................................................
Sitd Back Link Pointer999................................................................................................................................................................
Queue Element Transfer Descriptor (qtd)1000................................................................................................................................................................
Next Qtd Pointer1001................................................................................................................................................................
Alternate Next Qtd Pointer1001................................................................................................................................................................
Qtd Token1001................................................................................................................................................................
Qtd Buffer Page Pointer List1004................................................................................................................................................................
Queue Head1005................................................................................................................................................................
Queue Head Horizontal Link Pointer1005................................................................................................................................................................
Transfer Overlay1008................................................................................................................................................................
Periodic Frame Span Traversal Node (fstn)1009................................................................................................................................................................
Ftsn Normal Path Pointer1010................................................................................................................................................................
Fstn Back Path Link Pointer1010................................................................................................................................................................
Host Operations1010................................................................................................................................................................
Host Controller Initialization1011................................................................................................................................................................
Power Port1012................................................................................................................................................................
Reporting Over-current1012................................................................................................................................................................
Port Suspend/resume1013................................................................................................................................................................
Schedule Traversal Rules1015................................................................................................................................................................
Periodic Schedule Frame Boundaries Vs. Bus Frame Boundaries1016................................................................................................................................................................
Periodic Schedule1019................................................................................................................................................................
Managing Isochronous Transfers Using Itds1020................................................................................................................................................................
Host Controller Operational Model For Itds1021................................................................................................................................................................
Software Operational Model For Itds1022................................................................................................................................................................
Periodic Scheduling Threshold1024................................................................................................................................................................
Asynchronous Schedule1025................................................................................................................................................................
Adding Queue Heads To Asynchronous Schedule1026................................................................................................................................................................
Removing Queue Heads From Asynchronous Schedule1026................................................................................................................................................................
Empty Asynchronous Schedule Detection1028................................................................................................................................................................
Asynchronous Schedule Traversal: Start Event1029................................................................................................................................................................
Reclamation Status Bit (usbsts Register)1029................................................................................................................................................................
Managing Control/bulk/interrupt Transfers Via Queue Heads1029................................................................................................................................................................
Buffer Pointer List Use For Data Streaming With Qtds1030................................................................................................................................................................
Adding Interrupt Queue Heads To The Periodic Schedule1032................................................................................................................................................................
Managing Transfer Complete Interrupts From Queue Heads1032................................................................................................................................................................
Ping Control1033................................................................................................................................................................
Split Transactions1034................................................................................................................................................................
Split Transactions For Asynchronous Transfers1034................................................................................................................................................................
Split Transaction Interrupt1036................................................................................................................................................................
Split Transaction Scheduling Mechanisms For Interrupt1036................................................................................................................................................................
Host Controller Operational Model For Fstns1039................................................................................................................................................................
Software Operational Model For Fstns1041................................................................................................................................................................
Tracking Split Transaction Progress For Interrupt Transfers1042................................................................................................................................................................
Split Transaction Execution State Machine For Interrupt1042................................................................................................................................................................
Periodic Interrupt—do-start-split1043................................................................................................................................................................
Periodic Interrupt—do-complete-split1044................................................................................................................................................................
Managing The Qh[frametag] Field1047................................................................................................................................................................
Rebalancing The Periodic Schedule1048................................................................................................................................................................
Split Transaction Isochronous1048................................................................................................................................................................
Split Transaction Scheduling Mechanisms For Isochronous1049................................................................................................................................................................
Tracking Split Transaction Progress For Isochronous Transfers1053................................................................................................................................................................
Split Transaction Execution State Machine For Isochronous1054................................................................................................................................................................
Periodic Isochronous—do-start-split1055................................................................................................................................................................
Periodic Isochronous—do Complete Split1057................................................................................................................................................................
Complete-split For Scheduling Boundary Cases 2a, 2b1060................................................................................................................................................................
Split Transaction For Isochronous—processing Example1061................................................................................................................................................................
Port Test Modes1062................................................................................................................................................................
Transfer/transaction Based Interrupts1064................................................................................................................................................................
Transaction Error1064................................................................................................................................................................
Serial Bus Babble1064................................................................................................................................................................
Data Buffer Error1065................................................................................................................................................................
Usb Interrupt (interrupt On Completion (ioc)1066................................................................................................................................................................
Short Packet1066................................................................................................................................................................
Host Controller Event Interrupts1066................................................................................................................................................................
Port Change Events1066................................................................................................................................................................
Frame List Rollover1066................................................................................................................................................................
Interrupt On Async Advance1066................................................................................................................................................................
Host System Error1067................................................................................................................................................................
Device Data Structures1067................................................................................................................................................................
Endpoint Queue Head1068................................................................................................................................................................
Current Dtd Pointer1070................................................................................................................................................................
Setup Buffer1070................................................................................................................................................................
Endpoint Transfer Descriptor (dtd)1071................................................................................................................................................................
Device Operational Model1073................................................................................................................................................................
Device Controller Initialization1073................................................................................................................................................................
Port State And Control1075................................................................................................................................................................
Bus Reset1077................................................................................................................................................................
Suspend Description1078................................................................................................................................................................
Suspend Operational Model1078................................................................................................................................................................
Managing Endpoints1078................................................................................................................................................................
Endpoint Initialization1079................................................................................................................................................................
Data Toggle1080................................................................................................................................................................
Data Toggle Reset1080................................................................................................................................................................
Data Toggle Inhibit1080................................................................................................................................................................
Device For Packet Transfers1081................................................................................................................................................................
Priming Transmit Endpoints1081................................................................................................................................................................
Priming Receive Endpoints1081................................................................................................................................................................
Interrupt/bulk Endpoint Operational Model1082................................................................................................................................................................
Interrupt/bulk Endpoint Bus Response Matrix1083................................................................................................................................................................
Control Endpoint Operation Model1084................................................................................................................................................................
Setup Phase1084................................................................................................................................................................
Data Phase1084................................................................................................................................................................
Status Phase1085................................................................................................................................................................
Control Endpoint Bus Response Matrix1085................................................................................................................................................................
Isochronous Endpoint Operational Model1086................................................................................................................................................................
Isochronous Pipe Synchronization1087................................................................................................................................................................
Isochronous Endpoint Bus Response Matrix1088................................................................................................................................................................
Managing Queue Heads1088................................................................................................................................................................
Queue Head Initialization1089................................................................................................................................................................
Operational Model For Setup Transfers1089................................................................................................................................................................
Managing Transfers With Transfer Descriptors1090................................................................................................................................................................
Software Link Pointers1090................................................................................................................................................................
Building A Transfer Descriptor1090................................................................................................................................................................
Executing A Transfer Descriptor1091................................................................................................................................................................
Transfer Completion1092................................................................................................................................................................
Flushing/depriming An Endpoint1092................................................................................................................................................................
Device Error Matrix1093................................................................................................................................................................
Servicing Interrupts1093................................................................................................................................................................
High-frequency Interrupts1093................................................................................................................................................................
Low-frequency Interrupts1094................................................................................................................................................................
Error Interrupts1094................................................................................................................................................................
Deviations From The Ehci Specifications1094................................................................................................................................................................
Embedded Transaction Translator Function1095................................................................................................................................................................
Data Structures1096................................................................................................................................................................
Operational Model1096................................................................................................................................................................
Microframe Pipeline1097................................................................................................................................................................
Split State Machines1097................................................................................................................................................................
Asynchronous Transaction Scheduling And Buffer Management1098................................................................................................................................................................
Periodic Transaction Scheduling And Buffer Management1098................................................................................................................................................................
Multiple Transaction Translators1098................................................................................................................................................................
Device Operation1098................................................................................................................................................................
Non-zero Fields The Register File1099................................................................................................................................................................
Sof Interrupt1099................................................................................................................................................................
Embedded Design1099................................................................................................................................................................
Frame Adjust Register1099................................................................................................................................................................
Miscellaneous Variations From Ehci1099................................................................................................................................................................
Port Reset1099................................................................................................................................................................
Port Speed Detection1100................................................................................................................................................................
Timing Diagrams1101................................................................................................................................................................
C Interfaces1105................................................................................................................................................................
Transaction Protocol1114................................................................................................................................................................
Start Condition1114................................................................................................................................................................
Slave Address Transmission1115................................................................................................................................................................
Repeated Start Condition1116................................................................................................................................................................
Stop Condition1116................................................................................................................................................................
Protocol Implementation Details1116................................................................................................................................................................
Transaction Monitoring—implementation Details1116................................................................................................................................................................
Control Transfer—implementation Details1116................................................................................................................................................................
Address Compare—implementation Details1117................................................................................................................................................................
Arbitration Procedure1117................................................................................................................................................................
Arbitration Control1118................................................................................................................................................................
Clock Control1118................................................................................................................................................................
Clock Synchronization1119................................................................................................................................................................
Input Synchronization And Digital Filter1119................................................................................................................................................................
Input Signal Synchronization1119................................................................................................................................................................
Clock Stretching1119................................................................................................................................................................
Boot Sequencer Mode1119................................................................................................................................................................
Using The Boot Sequencer For Reset Configuration1120................................................................................................................................................................
Eeprom Data Format1120................................................................................................................................................................
Boot Sequencer Done Indication1123................................................................................................................................................................
Interrupt Service Routine Flowchart1123................................................................................................................................................................
Initialization Sequence1124................................................................................................................................................................
Generation Of Start1125................................................................................................................................................................
Post-transfer Software Response1125................................................................................................................................................................
Generation Of Stop1126................................................................................................................................................................
Generation Of Repeated Start1126................................................................................................................................................................
Slave Mode Interrupt Service Routine1126................................................................................................................................................................
Slave Transmitter And Received Acknowledge1126................................................................................................................................................................
Loss Of Arbitration And Forcing Of Slave Mode1127................................................................................................................................................................
Duart Overview1129................................................................................................................................................................
Duart Features1130................................................................................................................................................................
Duart Modes Of Operation1131................................................................................................................................................................
Duart External Signal Descriptions1131................................................................................................................................................................
Duart Signal Overview1131................................................................................................................................................................
Duart Detailed Signal Descriptions1131................................................................................................................................................................
Duart Memory Map/register Definition1132................................................................................................................................................................
Duart Register Descriptions1133................................................................................................................................................................
Receiver Buffer Registers (urbr1 And Urbr)1133................................................................................................................................................................
Transmitter Holding Registers (uthr1 And Uthr)1134................................................................................................................................................................
Divisor Most And Least Significant Byte Registers (udmb And Udlb)1134................................................................................................................................................................
Interrupt Enable Registers (uier1 And Uier)1136................................................................................................................................................................
Interrupt Id Registers (uiir1 And Uiir)1137................................................................................................................................................................
Fifo Control Registers (ufcr1 And Ufcr)1138................................................................................................................................................................
Alternate Function Registers (uafr1 And Uafr)1139................................................................................................................................................................
Line Control Registers (ulcr1 And Ulcr)1140................................................................................................................................................................
Modem Control Registers (umcr1 And Umcr)1142................................................................................................................................................................
Line Status Registers (ulsr1 And Ulsr)1142................................................................................................................................................................
Modem Status Registers (umsr1 And Umsr)1144................................................................................................................................................................
Scratch Registers (uscr1 And Uscr)1144................................................................................................................................................................
Dma Status Registers (udsr1 And Udsr)1145................................................................................................................................................................
Serial Interface1147................................................................................................................................................................
Start Bit1147................................................................................................................................................................
Data Transfer1147................................................................................................................................................................
Parity Bit1147................................................................................................................................................................
Stop Bit1148................................................................................................................................................................
Baud-rate Generator Logic1148................................................................................................................................................................
Local Loopback Mode1148................................................................................................................................................................
Framing Error1149................................................................................................................................................................
Parity Error1149................................................................................................................................................................
Overrun Error1149................................................................................................................................................................
Fifo Mode1149................................................................................................................................................................
Fifo Interrupts1149................................................................................................................................................................
Dma Mode Select1150................................................................................................................................................................
Interrupt Control Logic1150................................................................................................................................................................
Duart Initialization/application Information1150................................................................................................................................................................
Spi Transmission And Reception Process1155................................................................................................................................................................
Spi As A Master Device1155................................................................................................................................................................
Spi As A Slave Device1156................................................................................................................................................................
Spi In Multiple-master Operation1157................................................................................................................................................................
Spi Mode Register (spmode)1161................................................................................................................................................................
Spi Event Register (spie)1163................................................................................................................................................................
Spi Mask Register (spim)1164................................................................................................................................................................
Spi Command Register (spcom)1166................................................................................................................................................................
Spi Transmit Data Hold Register (spitd)1166................................................................................................................................................................
Spi Receive Data Hold Register (spird)1167................................................................................................................................................................
Reverse Mode Spmode[rev] Examples1167................................................................................................................................................................
Spi Master Programming Example1168................................................................................................................................................................
Spi Slave Programming Example1168................................................................................................................................................................
Jtag Overview1169................................................................................................................................................................
Jtag Signals1169................................................................................................................................................................
Jtag External Signal Descriptions1170................................................................................................................................................................
Jtag Registers And Scan Chains1171................................................................................................................................................................
Gpio Direction Register (gpdir)1175................................................................................................................................................................
Gpio Open Drain Register (gpodr)1175................................................................................................................................................................
Gpio Data Register (gpdat)1176................................................................................................................................................................
Gpio Interrupt Event Register (gpier)1176................................................................................................................................................................
Gpio Interrupt Mask Register (gpimr)1176................................................................................................................................................................
Gpio Interrupt Control Register (gpicr)1177................................................................................................................................................................
Appendix A Revision History1179................................................................................................................................................................
Byte Ordering1192................................................................................................................................................................

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