Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 960

Universal Serial Bus Interface
Offset 0x2_31A4
31 30 29
R
— DPIE 1msE BSEIE BSVIE ASVIE AVVIE IDIE
W
Reset
15 14 13
R DPS 1msT BSE
—
W
Reset 0 0 0
Bits Name
31 — Reserved, should be cleared.
30 DPIE Data pulse interrupt enable
1 Enable
0 Disable
29 1msE 1-millisecond timer Interrupt enable
1 Enable
0 Disable
28 BSEIE B session end interrupt enable
1 Enable
0 Disable
27 BSVIE B session valid interrupt enable
1 Enable
0 Disable
26 ASVIE A session valid interrupt enable
1 Enable
0 Disable
25 AVVIE A VBus valid interrupt enable
1 Enable
0 Disable
24 IDIE USB ID interrupt enable.
1 Enable
0 Disable
23 — Reserved, should be cleared.
22 DPIS Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only
detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0).
Software must write a one to clear this bit.
21 1msS 1-millisecond timer interrupt status. Set once every millisecond.
Software must write a one to clear this bit.
20 BSEIS B session end interrupt status. Set when VBus has fallen below the B session end threshold.
Software must write a one to clear this bit.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-32
28 27 26 25
12 11 10 9
BSV ASV AVV
0 1 1 0
Figure 16-21. OTG Status Control (OTGSC)
Table 16-24. OTGSC Register Field Descriptions
24 23 22 21
DPIS 1msS BSEIS BSVIS ASVIS AVVIS IDIS
—
w1c w1c
All zeros
8 7 5
ID
—
0 0 0 1
Description
Access: Mixed
20 19 18 17
w1c w1c w1c w1c
4 3 2 1
DP OT — VC
0 0 0 0
Freescale Semiconductor
16
w1c
0
VD
0