Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 436

DDR Memory Controller
9.5.4.1 Clock Distribution
• If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be
used. These buffers were designed for DDR applications.
• PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and
loading.
• DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.
CS[0]
MCK, MCK
Figure 9-26. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs
9.5.5 DDR SDRAM Mode-Set Command Timing
The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time.
Figure 9-27 shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
SDRAM Clock
MCS
MRAS
MCAS
MA n
MBA n
MWE
MDQ n
MDQS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-42
DDR
0 1 2 3
Code Code
0x4 0x0
Figure 9-27. DDR SDRAM Mode-Set Command Timing
A[13:0], BA[2:0], MRAS, MCAS, MWE, CKE
DQ[0:7], DQS[0], DM[0]
DQ[8:15], DQS[1], DM[1]
DQ[16:23], DQS[2], DM[2]
DQ[24:31], DQS[3], DM[3]
4 5 6 7 8 9 10 11 12
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