Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 829

Offset eTSEC1:0x2_4E00
0 1
R
ALM1P ALM2P —
W
Reset 0 0
16 17 18
R
RTPE FRD
W
Reset 0 0
Table 15-109 describes the fields of the TMR_CTRL register. Register fields not described below are
reserved.
Bits Name
0 ALM1P Alarm1 output polarity
0 active high output
1 active low output
1 ALM2P Alarm2 output polarity
0 active high output
1 active low output
3 FS FIPER start indication
0 Fiper is enabled through timer enable
1 Fiper is enabled through timer enable and alarm indication.
4 PP1L Fiper1 pulse loopback mode enabled.
0 Trigger1 input is based upon normal external trigger input.
1 Fiper1 pulse is looped back into Trigger1 input.
5 PP2L Fiper2 pulse loopback mode enabled.
0 Trigger2 input is based upon normal external trigger input.
1 Fiper2 pulse is looped back into Trigger2 input.
6–15 TCLK_ 1588 timer reference clock period. The timer clock counter will increment by TCLK_PERIOD every time
PERIOD the accumulator register overflows. This clock period must be larger than the clock period of the timer
reference clock. For applications where user does not want the clock period to be added, they can
program this field to 1 to count the clock ticks. This field defaulted to 1 to count overflow ticks.
For nanosecond granularity on 1588 timer counter rate, the TCLK_PERIOD should be calculated using
the following equation:
16 RTPE Record Tx Timestamp to PAL Enable.
When set, and FCB[PTP] is set, the 8-byte timestamp for the packet is written to the PAL located in
external memory location at an offset of 16 bytes from the start of the Data Buffer Pointer of the first
TxBD. For guidelines on using the RTPE bit, refer to
Transmit
17 FRD FIPER Realignment Disable
0 Fiper Realignment is enabled.
1 Fiper Realignment is disabled.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2 3 4 5
FS PP1L PP2L
0 0 0 0
19 20 21
ESFDP ESFDE ETEP2 ETEP1 COPH CIPH TMSR
0 0 0 0
Figure 15-105. TMR_CTRL Register Definition
Table 15-109. TMR_CTRL Register Field Descriptions
9
TCLK_PERIOD = 10 /Nominal_Frequency
Packets."
Enhanced Three-Speed Ethernet Controllers
6
TCLK_PERIOD
0 0 0 0
22 23 24 25
0 0 0 0
Description
Section 15.6.6.5, "Timestamp Insertion on
Access: Mixed
0 0 0 0 0
26 27 28 29 30
BYP TE CKSEL
0 0 0 0 0
15
1
31
1
15-111