Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 613

13.3.3.7 Subclass Code Configuration Register
Figure 13-25 shows the subclass code fields. This is the middle byte of the class code.
Offset 0x0A
7
R
W
Reset 0
Table 13-29 shows the bit settings of the subclass code register.
Table 13-29. Subclass Code Configuration Register Field Descriptions
Bits Name
7–0 SC
13.3.3.8 Base Class Code Configuration Register
Figure 13-26 shows the base class code fields. This is the upper byte of the class code.
Offset 0x0B
7
R
W
Reset 0
Table 13-30 shows the bit settings of the class code register.
Table 13-30. Class Code Configuration Register Field Descriptions
Bits Name
7–0 BCC
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
0 1
Figure 13-25. Subclass Code Configuration Register
Sub-class code. This field is hard-wired to 0x20, indicating a Power PC processor.
0 0
Figure 13-26. Base Class Code Configuration Register
Base class code. This field is hard-wired to 0x0B, indicating a processor.
SC
0 0
Description
BCC
0 1
Description
PCI Bus Interface
Access: Read-only
0 0
Access: Read-only
0 1
0
0
0
1
13-31