Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 985

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
dt Total Bytes to Transfer
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
1
Host controller read/write; all others read-only.
Queue element transfer descriptors must be aligned on 32-byte boundaries.
16.5.5.1 Next qTD Pointer
The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor.
Bits Name
31–5 Next qTD This field contains the physical memory address of the next qTD to be processed and corresponds to
Pointer memory address signals [31:5], respectively.
4–1 — Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
0 T Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
16.5.5.2 Alternate Next qTD Pointer
The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the
data stream to the next client buffer on short packet. To be more explicit the host controller will always use
this pointer when the current qTD is retired due to short packet.
Table 16-54. qTD Alternate Next Element Transfer Pointer (DWord 1)
Bits Name
31–5 Alternate Next
qTD Pointer
4–1 —
0 T
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Next qTD Pointer
Alternate Next qTD Pointer
1
Figure 16-40. Queue Element Transfer Descriptor (qTD)
Table 16-53. qTD Next Element Transfer Pointer (DWord 0)
This field contains the physical memory address of the next qTD to be processed in the event that
the current qTD execution encounters a short packet (for an IN transaction). The field corresponds
to memory address signals [31:5], respectively.
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
15 14 13 12 11 10 9
PID
1 1
ioc C_Page Cerr
Code
Description
Description
Universal Serial Bus Interface
8 7 6 5 4 3 2 1
0000
0000
1
Status
1
Current Offset
0000_0000_0000
0000_0000_0000
0000_0000_0000
0000_0000_0000
0 offset
T 0x00
T 0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
16-57