Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 995

16.5.7.1 FTSN Normal Path Pointer
The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any
valid periodic schedule data type.
Bits Name
31–5 NPLP Normal path link pointer. Contains the address of the next data object to be processed in the periodic list and
corresponds to memory address signals [31:5], respectively.
4–3 — Reserved, should be cleared. These bits must be written as 0s.
2–1 Typ Indicates to the host controller whether the item referenced is a iTD/siTD, QH, or FSTN. This allows the host
controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
0 T Terminate.
0 Link pointer is valid.
1 Link pointer field is not valid.
16.5.7.2 FSTN Back Path Link Pointer
The second DWord of an FTSN node contains a link pointer to a queue head. If the T-bit in this pointer is
a zero, then this FSTN is a Save-Place indicator. Its Typ field must be set by software to indicate the target
data structure is a queue head. If the T-bit in this pointer is set, then this FSTN is the Restore indicator.
When the T-bit is a one, the host controller ignores the Typ field.
Bits Name
31–5 BPLP Back path link pointer. Contains the address of a queue head. This field corresponds to memory address
signals [31:5], respectively.
4–3 — Reserved, should be cleared. These bits must be written as 0s.
2–1 Typ Software must ensure this field is set to indicate the target data structure is a Queue Head (01). Any other
value in this field yields undefined results.
0 T Terminate.
0 Link pointer is valid (that is, the host controller may use bits 31–5 (in combination with the
CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this
FSTN is a Save-Place indicator.
1 Link pointer field is not valid (that is, the host controller must not use bits 31–5 (in combination with the
CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this
FSTN is a Restore indicator.
16.6 Host Operations
The general operational model for the USB DR module in host mode is defined by the Enhanced Host
Controller Interface (EHCI) Specification. The EHCI specification describes the register-level interface
for a host controller for the USB Revision 2.0. It includes a description of the hardware/software interface
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-62. FTSN Normal Path Pointer
Table 16-63. FSTN Back Path Link Pointer
Description
Description
Universal Serial Bus Interface
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