Timing External Memory Accesses - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SDRAM Controller
tRC
Required delay between issuing successive bank activate commands to the
same SDRAM internal bank. This delay is not directly programmable.
The t delay is satisfied by programming the
RC
ensure that t
RAS
tRFC
Required delay between issuing an auto-refresh command and a bank acti-
vate command, and between issuing successive auto-refresh commands.
This delay is not directly programmable and is assumed to be equal to t
The t delay is satisfied by programming the
RC
ensure that t
RAS
tRRD
This is the required delay between a bank A activate command and a bank
B activate command. This delay is not programmable and fixed to
t + 1 cycles. This delay is used for multibank operation (ADSP-2137x
RCD
processors only).
tXSR
Required delay between exiting the self-refresh mode and issuing an
auto-refresh command. This delay is not directly programmable and is
assumed to be equal to t
t and t fields to ensure that t
RAS RP

Timing External Memory Accesses

The SDRAM controller is capable of running at up to 166 MHz and can
run at various frequencies, depending on the programmed SDRAM clock
( ) to core clock (
SDCLK
3-36
≥ t
+ t .
RP RC
≥ t
+ t .
RP RC
. The t
RC RC
RAS
) ratios. These are shown in
CCLK
ADSP-21368 SHARC Processor Hardware Reference
and
SDTRAS
and
SDTRAS
delay is satisfied by programming the
≥ t
+ t .
RP RC
fields to
SDTRP
.
RC
fields to
SDTRP
Table 3-13.