Texas Instruments OMAP5912 Reference Manual page 81

SPRU749A
support up to 64M bytes of address space through a 25-bit address
bus.
Note:
At the OMAP5912 level, two chip-selects can be split in half by configuration
to provide four chip-selects. This enables OMAP5912 to provide up to six
chip-selects supporting up to 32M bytes of address space on four
chip-selects and up to 64M bytes on two chip-selects.
L3 OCP-T1 and L3 OCP-T2 ports are provided to enable memory access
from the OMAP3.2 gigacell on a standard basis protocol. Only the L3
OCP-T1 is used in OMAP5912 to access the single SRAM memory.
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Emulator interface through JTAG port
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System DMA running at 96 MHz. It consists of:
J
Seventeen logical channels
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Seven physical ports + one for configuration
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Four physical channels
The ports are connected to the L3 OCP targets, the external memory, the
TIPB bridge, the MPUI, and one dedicated port connected to an LCD con-
troller. The system DMA controller can be controlled via the MPU private
TIPB or by an external host via the OCP-I port.
The system DMA controller is designed for low-power operation. It is parti-
tioned into several clock domains where each clock domain is enabled
only when it is used. All clocks are disabled when no DMA transfers are
active (synchronous to the MPU TIPB, this feature is totally under
hardware control; no specific programming is needed).
Five different logical channels types are supported, each one representing
a specific feature set:
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LCh−2D for memory to memory transfers, 1D and 2D
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LCh−P for peripheral transfers
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LCh−PD for peripheral transfers on a dedicated channel
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LCh−G for graphical transfers/operations
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LCh−D for display transfers
The available features are:
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Support for up to four address modes:
OMAP3.2 Features
OMAP3.2 Subsystem 23