Texas Instruments OMAP5912 Reference Manual page 89

SPRU749A
(synchronous flash or ASIC). The frequency must be set to comply with
the attached device's timing constraints in combination with the others
EMIFS timing controls.
-
In synchronous mode 4 −5, a retiming mode enables read data to be
latched by a delayed REF_CLK. This retiming mode must not be used with
asynchronous modes.
J
The REF_CLK delay is obtained through the IC I/O feedback of
FLASH.CLK to offer optimum data and clock alignment. Pipelined
access offers relaxed timing constraints.
J
The retiming mode is enabled through RT bit field in the CS
configuration register (See Table 19).
-
Memory control signal (CS, OE, WE, ADV, ADDRESS) setup and hold
timing can be controlled by programmable internal delay generation.
J
OE valid/invalid timing from/to CS and address valid/invalid is
programmable through OESETUP, OEHOLD bit field in the advanced
CS configuration register.
J
WE valid timing from CS, address, and data valid is programmable
through WRWST bit field in the CS configuration register. WE hold
time is fixed to one REF_CLK.
J
ADV valid pulse time is programmable through ADVHOLD bit field in
the advance CS configuration register.
H
In synchronous read mode, the ADV setup to REF_CLK rising
edge is controlled by the ADVHOLD bit field. The ADV hold time
from REF_CLK rising edge is fixed to one TC_CK.
J
Address setup and hold time with ADV control:
H
In synchronous mode, the address setup time from REF_CLK
rising edge (ADV valid) is controlled by ADVHOLD bit field.
H
In multiplexed synchronous mode, the address hold time from
REF_CLK rising edge is fixed to one REF_CLK from ADV invalid
time.
H
In asynchronous mode, the address setup time to ADV invalid is
controlled by ADVHOLD bit field.
H
In asynchronous mode, address hold time from ADV invalid is
fixed to one REF_CLK.
-
Read and write access time is controlled by programmable internal wait
state generation (non-full-handshaking mode). An external Ready input
Traffic Controller
OMAP3.2 Subsystem 31