Figure 7.
Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=4
FCLKDIV=1 OESETUP = 2 OEHOLD = 1 ADVHOLD = 0. Data write-back on the bus after
read completion.
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A(25:1)
FLASH.D(15:0)
FLASH.OE
FLASH_DIR_O
.FLASH.BE(1:0)
FLASH.RDY
SPRU749A
M cycles
OESETUP cycles
Low
N cycles
Valid address
Valid data D0
00
OMAP3.2 Subsystem
Traffic Controller
D0
OEHOLD
39