Texas Instruments OMAP5912 Reference Manual page 78

Multimedia processor device overview and architecture
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Introduction
Figure 1.
OMAP3.2 Gigacell
Endianism
conversion
DSP bus
Traffic
controller
ROM
16,32
S
SRAM
L
Flash
Slow
SBFlash
O
bus
W
I/F
F
16
SDRAM
A
S
Fast
bus
T
I/F
L3
32
L3/OCP-T1
O
(target)
C
P
I/F
L3
32
L3/OCP-T2
O
(target)
C
P
I/F
32
L3/OCP-I
L3/OCP
(initiator)
initiator
20
OMAP3.2 Subsystem
32
STIO
DSP
32
TIPB ports
DSP
MMU
MPUI port
32
MPU bus
32
32
Slow I/F DMA
32
Fast I/F DMA
32
32
L3/OCP-T1 DMA
32
L3/OCP-T2 DMA
32
ARM926EJS
plus IF logic
DSP timer 1
(32)
DSP timer 2
(32)
DSP timer 3
(32)
16
Endianism
conversion
MPUI
32
32
MPUI-DMA
Slow
port
port
Fast
port
TIPB
System
port
DMA
controller
OCP-T1
port
OCP-T2 LCD
TIPB
port
port
I/F
32
32
32
MPU
TIPB
MPU bus
LCD controller
16
32
To external
To LCD
LCD
display
controller
DSPINT
Mailbox
IF
DSP WD
timer
DSP
INTH
16
16
DSP TIPB
DPLL 1
CLKM 1
CLKM 2
CLKM 3
T
I
32
P
B
32
32
b
r
i
d
MPU TIPB
g
e
(2)
MPU
timer 1
32
(32)
MPU
timer 2
MPU
(32)
MPU
WD
INTH
timer
MPU
timer 3
(32)
ETM
Test and
configuration
DSP
TIPB
(private)
DSP
TIPB
(shared)
CLKIN
Clkout1
Clkout2
Reset
Clkout3
MPU
TIPB
(public)
MPU
TIPB
(private)
ETM
JTAG
SPRU749A

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