Texas Instruments OMAP5912 Reference Manual page 1138

Register Access Ry (ARDY)
Table 22. ARDY Set Conditions
Mode
Master transmit
Master receive
Master transmit or
receive
Slave transmit
Slave receive
No Acknowledgment (NACK)
SPRU760B
The LH is able to clear this bit only by writing a 1 into this register. Writing 0 has
no effect.
In interrupt mode, the LH needs to poll this bit after each read to I2C_DATA to
ensure that there is no other DATA on the FIFO waiting to be read. Indeed, the
RRDY needs to be cleared to 0 in order to receive a new RRDY interrupt.
If the DMA receive mode is enabled, this bit is not set. Instead, a DMA RX
request to the main DMA controller of the system is generated.
0: Receive buffer empty
-
1: Receive data ready (for read)
-
Value after reset is low.
When set to 1, this read-/clear-only bit indicates that the previously
programmed data and command (receive or transmit, master or slave) has
been performed and the status bit has been updated. The LH uses this flag to
2
let it know that the I C registers are ready to be accessed again (see Table 22).
Others ARDY Set Conditions
STP = 1 DCOUNT = 0
STP = 1 DCOUNT = 0 and receiver FIFO empty
STP = 0 DCOUNT passed 0
− Stop or restart condition received from master
− Stop or restart condition and receiver FIFO empty
The LH is able to clear this bit only by writing a 1 into this register. Writing 0 has
no effect.
0: No action
-
1: Access ready
-
Value after reset is low.
The read-/clear-only NO_ACKNOWLEDGE flag bit is set when the hardware
detects NO_ACKNOWLEDGE has been received.
I2C Multimaster Peripheral
Serial Interfaces 73