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Table 27. I
C System Configuration Register(I2C_SYSC)
Bit
Name
15:2
−
1
SRST
0
−
Soft Reset (SRST)
SPRU760B
When written, this register contains the byte(s) value(s) to transmit over the
2
I
C data line (1or 2 bytes). This register must be accessed 16-bit-wise, except
for the last byte in case of an odd number of bytes to transmit. The last byte
of the data packet can be written using a byte write access or a 16-bit-wise
access. In the 16-bit-wise access, the module transmits only the relevant byte,
based on the byte counter (I2C_CNT). This feature is useful for DMA access,
which supports only one word size per channel.
In SYSTEST loopback mode (I2C_SYSTEST:TMODE = 11), this register is
also the entry/receive point for the data.
Values after reset are low (all 16-bits).
A read access when the buffer is empty returns the previous read data value.
A write access when the buffer is full is ignored. In both events, the FIFO
pointers are not updated and a remote access error (hardware error) is
generated (access qualifier). No remote error is generated if the local host
performs a 16-bit access if the buffer contains a single byte.
Description
Reserved
Soft Reset
Reserved
When this bit is set to 1, all of the module is reset, as for the hardware reset.
The core automatically sets this bit to 0, and it is only reset by the hardware
reset. During reads, it always returns 0.
0: Normal mode
-
1: The module is reset
-
Values after reset is low.
I2C Multimaster Peripheral
Serial Interfaces
77
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