Texas Instruments OMAP5912 Reference Manual page 1135

Multimedia processor device overview and architecture
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I2C Multimaster Peripheral
Bus Busy (BB)
Receive Overrun (ROVR)
70
Serial Interfaces
Note:
When SBD = 1, in little-endian data format (I2C_CON:BE = 0), the MSB
reads as 0x00, and in big-endian format (I2C_CON:BE = 1), the LSB reads
as 0x00.
Whenever the number of bytes to be received is unknown (for example,
slave receiver), the LH must poll this bit before clearing the register access
ready interrupt flag.
0: No action
-
1: Single valid byte in last 16-bit data read
-
Value after reset is low.
This read-only bit indicates the state of the serial bus.
In slave mode, on reception of a start condition, the device sets BB to 1. BB
is cleared to 0 after reception of a stop condition.
In master mode, the software controls BB. To start a transmission with a start
condition, MST, TRX, and STT must be set to 1 in the I2C_CON register. To
end a transmission with a stop condition, STP must be set to 1 in the I2C_CON
register. When BB = 1, and STT is set to a 1, a restart condition is generated.
0: Bus is free
-
1: Bus is occupied
-
Value after reset is low.
Receive mode only.
This read-only bit indicates whether the receiver has experienced overrun.
Overrun occurs when the shift register is full and the receive FIFO is full. An
overrun condition does not result in a data loss; the peripheral is just holding
the bus (low on SCL) to prevent others bytes from being received.
ROVR is set to 1 when the I
ROVR is clear when reading the I2C_DATA register, or when resetting the I
(I2C_CON:I2C_EN = 0).
2
C recognizes an overrun.
2
C
SPRU760B

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