Texas Instruments OMAP5912 Reference Manual page 1129

I2C Multimaster Peripheral
Figure 22. Arbitration Procedure Between Two Master Transmitters
2
2.6.2 I C Clock Generation and I
64 Serial Interfaces
Bus line
SCL
Data
1
from
device 1
Data
1
from
device 2
Bus line
1
SDA
2
C Clock Synchronization
Under normal conditions, only one master device generates the clock signal,
SCL. During the arbitration procedure, however, two or more master devices
and the clock must be synchronized so that the data output can be compared.
The wired-AND property of the clock line means that a device that first
generates a low period of the clock line overrules the other devices. At this
high/low transition, the clock generators of the other devices are forced to start
generation of their own low period. The clock line is then held low by the device
with the longest low period, while the other devices that finish their low periods
must wait for the clock line to be released before starting their high periods.
A synchronized signal on the clock line is thus achieved, where the slowest
device determines the length of the low period and the fastest the length of the
high period.
If a device pulls down the clock line for a longer time, the result is that all clock
generators must enter the WAIT state. In this way, a slave can slow down a
fast master, and the slow device can create enough time to store a received
byte or prepare a byte to be transmitted. Figure 23 illustrates the clock
synchronization.
Device 1 loses arbitration
and switches off.
0 1
0 0 1
0 0 1
0 1
0 1
SPRU760B