Texas Instruments OMAP5912 Reference Manual page 1134

Table 21. Status Register(I2C_STAT)
Bit Name
15 SBD
14:13 −
12 BB
11 ROVR
10 XUDF
9 AAS
8:6 −
5 GC
4 XRDY
3 RRDY
2 ARDY
1 NACK
0 AL
Single Byte Data (SBD)
SPRU760B
0: Interrupt disabled
-
1: Interrupt enabled
-
Value after reset is low (all bits).
Description
Single byte data
Reserved
Bus busy
Receive overrun
Transmit underflow
Address as slave
Reserved
General call
Transmit data ready
Receive data ready
Register access ready
No acknowledgment interrupt enable
Arbitration lost interrupt enable
This register is composed of read-only and read-/clear-only registers. It
provides core status information for interrupt handling and other I
management.
This read-only bit is set to 1 in slave-receive or master-receive modes when
the last byte that was read from the I2C_DATA register contains a single valid
byte.
The core clears this bit to 0 when the local host clears the register access ready
interrupt flag.
I2C Multimaster Peripheral
2
C control
Serial Interfaces 69