Texas Instruments OMAP5912 Reference Manual page 1140

Table 24. Buffer Configuration Register(I2C_BUF)
Bit Name
15 RDMA_EN
14:8 −
7 XDMA_EN
6:0 −
Receive DMA Channel Enable (RDMA_EN)
Transmit DMA Channel Enable (XDMA_EN)
Table 25. Data Counter Register(I2C_CNT)
Bit Name
15:0 DCOUNT
SPRU760B
Value after reset is low.
Description
Receive DMA channel enable
Reserved
Transmit DMA channel enable
Reserved
This R/W register enables DMA transfers.
When this bit is set to 1, the receive DMA channel is enabled and the core
forces the receive data ready status bit (I2C_STAT:RRDY) to 0.
0: Receive DMA channel disabled
-
1: Receive DMA channel enabled
-
Value after reset is low.
When this bit is set to 1, the transmit DMA channel is enabled and the core
forces the transmit data ready status (I2C_STAT:XRDY) bit to 0.
0: Transmit DMA channel disabled
-
1: Transmit DMA channel enabled
-
Value after reset is low.
Description
Data count
This R/W register controls the numbers of bytes in the I
I2C Multimaster Peripheral
2
C data payload.
Serial Interfaces 75