Texas Instruments OMAP5912 Reference Manual page 1133

I2C Multimaster Peripheral
Module Revision Number (REV)
Table 20. Interrupt Enable Register(I2C_IE)
Bit Name
15:6 −
5 GC_IE
4 XRDY_IE
3 RRDY_IE
2 ARDY_IE
1 NACK_IE
0 AL_IE
68 Serial Interfaces
This read-only register contains the hard-coded revision number of the
module. A write to this register has no effect.
This 8-bit field indicates the revision number of the current I
module. Its value is fixed by hardware and corresponds to the RTL revision of
this module.
The 4 LSBs indicate a minor revision. The 4 MSBs indicate a major revision.
For example:
0x20: Revision 2.0
-
0x21: Revision 2.1
-
A reset has no effect on the value returned.
Note:
2
I C controller with interrupt using interrupt vector register (I2C_IV) is revision
1.x.
2
I C controller with interrupt using status register bits (I2C_STAT) is revision
2.x.
Description
Reserved
General call interrupt enable
Transmit data ready interrupt enable
Receive data ready interrupt enable
Register access ready interrupt enable
No acknowledgment interrupt enable
Arbitration lost interrupt enable
This R/W register controls the interrupts mask/unmask function.
The following are common to all bits:
When the local host sets a bit location to 1 , an interrupt is signaled to the local
host if the corresponding bit location in I2C_STAT (status register) is asserted
to 1 by the core of the I
is not signaled to the local host.
2
C controller. If it is set to 0, the interrupt is masked and
2
C controller
SPRU760B