Table of Contents
Advertisement
I2C Multimaster Peripheral
2.6.6
DMA Events
2.7
Register Map
66
Serial Interfaces
No-acknowledge interrupt (NACK): Generated when the master I
-
not receive an acknowledge from the receiver.
General call interrupt (GC): Generated when the device detects the
-
address of all zeros (8 bits).
Registers-ready-for-access interrupt (ARDY): Generated by the I
-
the previously programmed address, data, and command have been
performed and the status bits have been updated. This interrupt is used
to let the LH know that the I
Receive interrupt/status (RRDY): Generated when there is received data
-
ready to be read by the LH from the I2C_DATA register. The LH can poll
this bit to read the received data from the I2C_DATA register.
Transmit interrupt/status (XRDY): Generated when the LH needs to put
-
more data in the I2C_DATA register after the transmitted data has been
shifted out on the SDA pin. The LH can poll this bit to write the next
transmitted data into the I2C_DATA register.
When the interrupt signal is activated, the local host must read the I2C_STAT
register to define the type of interrupt, process the request, and then write into
this register the right value to clear the interrupt flag.
2
The I
C module can generate two DMA requests events, read (I2C_DMA_RX)
and write (I2C_DMA_TX), that the DMA controller can use to synchronously
read received data from the I2C_DATA and write transmitted data to the
I2C_DATA register. The DMA read and write requests are generated in a
similar manner as RRDY and XRDY, respectively.
2
The I
C DMA request signals (I2C_DMA_TX and I2C_DMA_RX) are activated
for every new 16-bit word to be read or written in the FIFOs.
Table 18 lists the revision, interrupt enable, I
configuration, data counter, and data access registers. Table 19 through
Table 26 describe the register bits.
Start address: FFFB 3800
2
C registers are ready for access.
2
C status, system status, buffer
2
C does
2
C when
SPRU760B
Advertisement
Chapters
Table of Contents
