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I2C Multimaster Peripheral
2
Figure 21.
I
C Data Transfer Formats
1
7
S
Slave address
1
7
S
Slave address 1st 7-bit
1 1 1 1 0 X X
1
7
S
Slave address
R/W ACK
Master Transmitter
Master Receiver
62
Serial Interfaces
1
1
R/W
ACK
(a) 7-Bit addressing format
1
1
R/W
ACK
Slave address 2nd 7-bit
0
(W)
(b) 10-Bit addressing format
1
1
8
Data
ACK
Any number
of bytes
(c) Addressing Format With Repeated Start Condition
In this mode, data assembled in one of the previously described data formats
is shifted out on the serial data line SDA in synch with the self-generated clock
pulses on the serial clock line SCL. The clock pulses are inhibited and SCL is
held low when the intervention of the processor is required (XUDF) after a byte
has been transmitted.
This mode can be entered only from the master transmitter mode. With any
of the address formats (Figure 21 (a), (b), and (c)), the master receiver is
entered after the slave address byte and bit R/W_ have been transmitted, if
R/W_ is high. Serial data bits received on bus line SDA are shifted in synch with
the self-generated clock pulses on SCL. The clock pulses are inhibited and
SCL held low when the intervention of the processor is required (ROVR) after
a byte has been transmitted. At the end of a transfer, it generates the stop
condition.
8
1
Data
ACK
8
1
ACK
7
1
1
S
Slave address
8
1
Data
ACK
8
1
Data
ACK
1
8
R/W ACK
Data
ACK
Any number
of bytes
SPRU760B
1
S
1
S
1
1
S
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