Jtag Instruction Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

JTAG Functionality
As an extension to the JTAG standard, the
additional debugging functions:
• The
TMS
as an emulation exception pin. An emulation exception is issued on
every rising edge of the
functionality in JTAG.
TMS
• The
EMU
if the
EMUOE
following indications:
• On watchpoint event no exception (
is 00.
• The
Whenever the TigerSHARC processor is in emulation mode
and ready for a new instruction line driven into the
register, the
is inserted. For more information, see "Emulation Mode"
on page 3-3.

JTAG Instruction Register

The JTAG Instruction register is five bits long and allows the Test Access
Port (TAP) controller to select any of the scannable data registers. The
LSB is the first to be shifted out through the
Instruction register follows the TigerSHARC processor implementation.
Data Registers
The Data registers are selected via the Instruction register. Once a particu-
lar Data register's value is written into the Instruction register, and the
TAP state is changed to
the TigerSHARC processor depends on the definition of the Data register
selected. See the IEEE 1149.1 specification for more details.
9-14
pin (when bit in the
TEME
TMS
output is an open drain signal (for wired OR) driven only
bit in the
EMUCTL
is pulled down for 20
EMU
pin is driven low until such an instruction
EMU
, the particular data going in and out of
SHIFT-DR
and
TMS EMU
register is set) functions
EMUCTL
signal. This function is in addition to
register is set. The
EXtype
cycles.
CCLK
. The encoding of this
TDO
ADSP-TS101 TigerSHARC Processor
pins have these
pin gives the
EMU
field in
WPiCTL)
EMUIR
Hardware Reference