D.3 Instruction Register - Analog Devices ADSP-2106x SHARC User Manual

JTAG Test Access Port
D.3 INSTRUCTION REGISTER
The instruction register allows an instruction to be shifted into the
processor. This instruction selects the test to be performed and/or the
test data register to be accessed. The instruction register is 5 bits long
with no parity bit. A value of 10000 binary is loaded (LSB nearest TDI)
into the instruction register whenever the TAP reset state is entered.
Table D.1 lists the binary code for each instruction. Bit 0 is nearest TDI
and bit 4 is nearest TDO. An "x" specifies a "don't-care" state. No data
registers are placed into test modes by any of the public instructions.
The instructions affect the ADSP-2106x as defined in the 1149.1
specification. The optional instructions RUNBIST, IDCODE and
USERCODE are not supported by the ADSP-2106x.
Instruction
Bits Instruction
4 3 2 1 0 Name
1 x x x x BYPASS
0 0 0 0 0 EXTEST
0 0 0 0 1 SAMPLE/PRELOAD
0 0 0 1 0 reserved for emulation
0 0 0 1 1 INTEST
0 0 1 0 0 reserved for emulation
0 0 1 0 1 reserved for emulation
0 0 1 1 0 reserved for emulation
0 0 1 1 1 reserved for emulation
0 1 x x x reserved for emulation
Table D.1 Test Instructions
The entry under "Register" is the serial scan path, either Boundary or
Bypass in this case, enabled by the instruction. Figure D.1 (on the next
page) shows these register paths. The 1-bit Bypass register is fully
defined in the 1149.1 specification. The Boundary register is described
in the next section.
No special values need be written into any register prior to selection of
any instruction. As Table D.1 shows, certain instructions are reserved
for emulator use. See Section D.7 for more information.
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Register
(Serial Path) Type
Bypass Public
Boundary Public
Boundary Public
— Private
Boundary Public
— Private
— Private
— Private
— Private
— Private
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