Register File Instruction Summary - Analog Devices ADSP-BF53x Blackfin Reference

Register File Instruction Summary

Table 2-1 lists the register file instructions. In
ing of these symbols:
• Allreg denotes:
B[3:0], L[3:0], A0.X, A0.W, A1.X, A1.W, ASTAT, RETS, RETI,
RETX, RETN, RETE, LC[1:0], LT[1:0], LB[1:0], USP, SEQSTAT
SYSCFG, CYCLES,
• An denotes either ALU Result register
• Dreg denotes any Data Register File register.
• Sysreg denotes the system registers:
,
RETX RETN
CYCLES2.
• Preg denotes any Pointer register,
• Dreg_even denotes
• Dreg_odd denotes
• DPreg denotes any Data Register File register or any Pointer regis-
ter, , or
FP
• Dreg_lo denotes the lower 16 bits of any Data Register File
register.
• Dreg_hi denotes the upper 16 bits of any Data Register File
register.
• An.L denotes the lower 16 bits of Accumulator
• An.H denotes the upper 16 bits of Accumulator
• Dreg_byte denotes the low order 8 bits of each Data register.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
R[7:0], P[5:0], SP, FP, I[3:0], M[3:0],
and
CYCLES2.
, , or ,
RETE RETS LC[1:0]
R0,R2,R4,
R1,R3,R5,
register.
SP
Computational Units
Table 2-1, note the mean-
or .
A0 A1
,
ASTAT SEQSTAT
, ,
LT[1:0] LB[1:0]
, or register.
FP SP
or
R6.
or
R7.
A0.W
,
, , ,
SYSCFG RETI
, , and
CYCLES
or .
A1.W
or .
A0.W A1.W
2-9