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Booting
The AC specification and bus interface are defined in reference to the
. (See the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet
SCLK
for the full AC specification.) The internal
input by a Phase Locked Loop (PLL).
SCLK
The
is an input to the internal clock driver—
LCLK
internal clock of the core, internal buses, memory, links, and most of the
chip's internal parts. The
phase locked. The
. The clock multiplication can be 2, 2.5, 3, 3.5, 4, 5, and 6.
CCLK
Systems must connect both
an integer
LCLKRAT
operation (important for SIMD operation and for fault tolerant systems).
Booting
The internal memory of the TigerSHARC processor can be loaded from
an 8-bit EPROM using a boot mechanism at system power up. The Tiger-
SHARC processor can also be booted using another master or through one
of the link ports. Selection of the boot source is controlled by external
pins.
Emulation and Test Support
The TigerSHARC processor supports the IEEE standard 1149.1 Joint
Test Action Group (JTAG) standard for system test. This standard defines
a method for serially scanning the I/O status of each component in a sys-
tem. The JTAG serial port is also used by the TigerSHARC processor
EZ-ICE® to gain access to the processor's on-chip emulation features.
1-24
is generated by a PLL from
CCLK
pins define the clock multiplication of
LCLKRAT
and
LCLK
(2, 3, 4, 5, or 6) guarantees predictable cycle-by-cycle
ADSP-TS101 TigerSHARC Processor
is phase locked to the
SCLK
. The
CCLK
to the same clock source. Using
SCLK
Hardware Reference
is the
CCLK
and is
LCLK
to
LCLK
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