Jtag Interface Pins - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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Processor Pin Descriptions

• In output mode, if the same flag is mapped to both data pins and

DPI pins, then the output comes from both pins.

• In input mode, if the same flag is mapped to both data pins and

DPI pins, the input from data pins is given priority.

• In input mode, if the same flag is mapped to both upper and lower

data pins, the input from the lower data pins is given priority.

RESETOUT/CLKOUT/RUNRSTIN

The default behavior of the

that allows the PLL to lock. In PLL bypass mode, where the

= 11, this pin functions as a

als and memory. This can also be accomplished by setting (= 1) bit 12

) in the power management control register and this functional-

ity applies to all ADSP-21367/8/9 and ADSP-2137x processors. Finally,

on the ADSP-2137x processors only, the

provide a running reset.

(ADSP-2137x)" on page 14-22.

JTAG Interface Pins

The JTAG test access port (TAP) consists of the

pins. The JTAG port can be connected to a controller that performs

a boundary scan for testing purposes. This port is also used by the Analog

Devices DSP Tools product line of JTAG emulators and development

software to access on-chip emulation features. To allow the use of the

emulator, a connector for its in-circuit probe must be included in the tar-

signal to clock synchronous peripher-

For more information, see "Running Reset

ADSP-21368 SHARC Processor Hardware Reference

pin is to provide a 4096 cycle delay

pin can configured to