Cache Disable & Cache Freeze - Analog Devices ADSP-2106x SHARC User Manual

Program Sequencing
3.10.3 Cache Disable & Cache Freeze
Freezing the cache prevents any changes to its contents—a cache miss
will not result in a new instruction being stored in the cache. Disabling
the cache stops its operation completely; all instruction fetches
conflicting with program memory data accesses are delayed by the
access. These functions are selected by the CADIS (cache enable/
disable) and CAFRZ (cache freeze) bits in the MODE2 register:
MODE2
Bit Name Function
4 CADIS Cache Disable
19 CAFRZ Cache Freeze
After reset the cache is cleared, containing no instructions, and is
unfrozen and enabled.
An instruction containing a program memory data access must not be
placed directly after a cache enable or cache disable instruction—the
ADSP-2106x must wait at least one cycle before executing the PM data
access. A NOP may be inserted to accomplish this.
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