Master Mode Operation - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SPI General Operations

Master Mode Operation

When the SPI is configured as a master, configure the SPI port and start
transfers using the following steps:
1. Before enabling the SPI port, programs should specify which of the
slave-select signals to use, setting one or more of the required SPI
flag select bits (
2. Write to the
a master and configuring the SPI system by specifying the appro-
priate word length, transfer format, baud rate, and other necessary
information.
When
CPHASE
controlled by the SPI port. When
controlled by the core and the user software has to control the pins
through the
slave-select signals), activate the desired slaves by clearing one or
more of the SPI flag bits (
3. Initiate the SPI transfer. The trigger mechanism for starting the
transfer is dependant upon the
See "Master Transfer Preparation" on page 6-18
The SPI generates the programmed clock pulses on
data is shifted out of
Before starting to shift, the
of the
TXSPIx
the
RXSR
With each new transfer initiate command, the SPI continues to
send and receive words, according to the SPI transfer mode (
bit in the
page 6-18
6-10
) in the
DSxEN
and
SPICTLx SPIBAUDx
is set to 0, the slave-select signals are automatically
bits. If
SPIFLGx
SPIFLGx
and shifted in from
MOSI
registers. At the end of the transfer, the contents of
register are loaded into the
registers). See
SPICTLx
for more details.
ADSP-21368 SHARC Processor Hardware Reference
registers.
SPIFLGx
registers, enabling the device as
= 1, the slave selects are
CPHASE
= 1 (user-controlled,
CPHASE
) in the
SPIFLGx
bits in the
TIMOD
register is loaded with the contents
TXSR
registers.
RXSPIx
"Master Transfer Preparation" on
registers.
registers.
SPICTLx
for details.
. The
SPICLK
simultaneously.
MISO
TIMOD