Data Transfers; Status Information - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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The endian format (LSB versus MSB first) is selectable by the
the
register (see
SPCTL
Data packing of two serial words into a 32-bit word is also selectable. The
bit in the
PACK
Unpacking" on page 5-45

Data Transfers

Serial port data is transferred using two different methods:
• DMA transfers
• Core-driven single word transfers
DMA transfers can be set up to transfer a configurable number of serial
words between the SPORT buffers (
and internal memory automatically. For more information on Sport DMA
operations, see DMA Block transfers section on
on page
5-73. Core-driven transfers use SPORT interrupts to signal the
processor core to perform single word transfers to/from the SPORT buff-
ers (
,
TXSPxA
TXSPxB
page 5-72
for more details.

Status Information

Serial ports provide status information about data buffers through the
and
DXS_A
DXS_B
in the
register. See
SPCTLx
page 5-59
for more details.
Depending on the
or
TXSPxy
RXSPxy
ADSP-21368 SHARC Processor Hardware Reference
"Endian Format" on page 5-45
register controls this option. See
SPCTL
for more details.
,
, and
RXSPxA
status bits and error status through the
"Serial Port Control Registers (SPCTLx)" on
setting, these bits reflect the status of either the
SPTRAN
data buffers.
,
TXSPxA
TXSPxB
"DMA Block Transfers"
). See
"SPORT Interrupts" on
RXSPxB
Serial Ports
bit of
LSBF
for more details).
"Data Packing and
,
, and
RXSPxA
RXSPxB
or
ROVF
TUVF
5-15
)
bits

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