Slave Mode Address Register; Slave Mode Status Register; Master Mode Control Register; Master Mode Address Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Register Descriptions

Slave Mode Address Register

The TWI slave mode address register (
address, which is the valid address that the slave-enabled TWI controller
responds to. The TWI controller compares this value with the received
address during the addressing phase of a transfer.
see "Slave Address Register (TWISADDR)" on page A-135.

Slave Mode Status Register

During and at the conclusion of slave mode transfers, the TWI slave mode
status register (
erally, slave mode status bits are not associated with the generation of
interrupts. Master mode operation does not affect slave mode status bits.
For more information, see "Slave Status Register (TWISSTAT)" on
page A-135.

Master Mode Control Register

The TWI master mode control register (
ated with master mode operation. Bits in this register do not affect slave
mode operation and should not be modified to control slave mode func-
tionality. For more information, see "Master Control Register
(TWIMCTL)" on page A-136.

Master Mode Address Register

During the addressing phase of a transfer, the TWI controller, with its
master enabled, transmits the contents of the TWI master mode address
register (
TWIMADDR
bit. That is, only the upper 7 bits that make up the slave address should be
written to this register. For example, if the slave address is 1010000, then
the
TWI_MASTER_ADDR
sponds to 0x50. When sending out the address on the bus, the TWI
12-6
) holds information on the current transfer. Gen-
TWISSTAT
). When programming this register, omit the read/write
register is programmed with 1010000, which corre-
ADSP-21368 SHARC Processor Hardware Reference
) holds the slave mode
TWISADDR
For more information,
) controls the logic associ-
TWIMCTL