Boundary-Scan Architecture - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Boundary-Scan Architecture

Full details of the JTAG standard can be found in the document IEEE
Standard Test Access Port and Boundary-Scan Architecture, ISBN
1-55937-350-4.
Boundary-Scan Architecture
The boundary-scan test logic consists of:
• A TAP comprised of five pins (see
• A TAP controller that controls all sequencing of events through the
test registers
• An Instruction register (
to select the test mode that performs the desired test operation
• Several data registers defined by the JTAG standard
Table B-1. Test Access Port Pins
Pin Name
TDI
TMS
TCK
TRST
TDO
The TAP controller is a synchronous, 16-state, finite-state machine con-
trolled by the
TCK
diagram occur on the rising edge of
pin, here denoted by either a logic 1 or logic 0 state. For full details of
TMS
the operation, see the JTAG standard.
B-2
) that interprets 5-bit instruction codes
IR
Input/Output
Input
Input
Input
Input
Output
and pins. Transitions to the various states in the
TMS
ADSP-BF537 Blackfin Processor Hardware Reference
Table B-1)
Description
Test Data Input
Test Mode Select
Test Clock
Test Reset
Test Data Out
and are defined by the state of the
TCK