Figure 24. Interleaved Priority
3.
Perform another FFT. The spur should disappear.
MSBs MISSING FROM TIME DOMAIN
Figure 25. Incorrect Bit Mask Setting
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
Scenario: The two MSBs are missing from the time domain plot.
1.
If evaluating the AD9200, AD9201, AD9280, or AD9281,
make sure the appropriate bits are selected under Config >
Bits > Data Bits. Bits 13 to 4 should be selected for the
AD9200 and AD9201. Bits 13 to 6 should be selected for
the AD9280 and AD9281. Default configuration files for
these ADCs are installed with ADC Analyzer.
2.
Make sure the bits are switching at the FIFO connector.
UPGRADING FIFO MEMORY
The FIFO evaluation board includes one or two 32 kB FIFOs,
depending on the model. Pin compatible FIFO upgrades
(64 kB to 256 kB) are available from Integrated Device
Technology, Inc. (IDT). The IDT part numbers are:
• IDT72V283: 32 kB (included)
• IDT72V293: 64 kB
• IDT72V2103: 132 kB
• IDT72V2113: 256 kB
For more information, visit
Rev. 0 | Page 25 of 44
www.idt.com
Need help?
Do you have a question about the HSC-ADC-EVALA-SC and is the answer not in the manual?