Table of Contents
Advertisement
11 System Design
Pin
Bus-Master-Independent:
REDY (o/d)
DMAR1
DMAR2
ID
2-0
RPBA
CPA
(o/d)
EBOOT
LBOOT
BMS
CLKIN
RESET
Serial Ports & Link Ports:
DTx
DRx
TCLKx
RCLKx
TFSx
RFSx
LxDAT 3-0
LxCLK
LxACK
JTAG Interface:
TCK
TMS
TDI
TDO
TRST
EMU
Table 11.1 ADSP-2106x Pin States At
11.2.3
RESET
RESET
The ADSP-2106x receives its clock input on the CLKIN pin. The
processor uses an on-chip phase-locked loop to generate its internal
clock. Because the phase-locked loop requires some time to achieve
phase lock, CLKIN must be valid for a minimum time period during
reset before the
specified in the ADSP-2106x Data Sheet.
RESET
must be asserted (low) at system powerup.
11 – 10
www.BDTIC.com/ADI
Type
State During & After RESET
O
Tristate
I
Input
I
Input
I
Inputs
I/S
Input
I/O
Tristate
I
Input
I
Input (must be tied to GND on the ADSP-21061)
I/O/T
Input
I
Input
I/A
Input
O
Tristate (for multichannel)
I
Input
I/O
Tristate
I/O
Tristate
I/O
Tristate
I/O
Tristate
I/O
Tristate (NC on the ADSP-21061)
I/O
Tristate(NC on the ADSP-21061)
I/O
Tristate(NC on the ADSP-21061)
I
Input
I/S
Input
I/S
Input
O
Tristate
I/A
Input
O
Tristate
RESET
RESET
& CLKIN
RESET
signal can be deasserted; this time period is
(cont.)
Advertisement
Table of Contents
Need help?
Do you have a question about the ADSP-2106x SHARC and is the answer not in the manual?
Questions and answers